Distributed Processing Architecture With Scalable Processing Layers
First Claim
1. A media processor for the processing of media based upon instructions, comprising:
- a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another;
at least one processing unit in at least one of said processing layers performing line echo cancellation functions on received data;
at least one processing unit in at least one of said processing layers performingencoding or decoding functions on received data; and
a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to said processing layers.
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Abstract
The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks. The hardware system architecture of the said novel gateway is comprised of a plurality of DPLPs, referred to as Media Engines that are interconnected with a Host Processor or Packet Engine, which, in turn, is in communication with interfaces to networks. Each of the PUs within the processing layers of the Media Engines are specially designed to perform a class of media processing specific tasks, such as line echo cancellation, encoding or decoding data, or tone signaling.
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Citations
22 Claims
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1. A media processor for the processing of media based upon instructions, comprising:
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a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another; at least one processing unit in at least one of said processing layers performing line echo cancellation functions on received data; at least one processing unit in at least one of said processing layers performing encoding or decoding functions on received data; and a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to said processing layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A media gateway for the processing of data and communication of data across a plurality of networks, comprising:
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a plurality of media processors, each of said media processors having a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another, wherein at least one processing unit in at least one of said processing layers performs echo cancellation functions on received data, wherein at least one processing unit in at least one of said processing layers performs encoding or decoding functions on received data, and wherein a task scheduler is adapted to receive a plurality of tasks from a source and distribute said tasks to the processing layers; a plurality of packet processors in communication with at least one of said media processors wherein the packet processor is adapted to packetize processed data, and a host processor in communication with at least one said packet or media processors.
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13. A method for processing media based upon instructions, comprising the steps of:
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receiving said media through a data interface; scheduling the processing of said media through a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to a plurality of processing layers; and processing said media in the plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another. - View Dependent Claims (14, 15, 16, 17)
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18. A distributed processing system implemented on a single chip having a total memory capacity comprising at least two processing layers wherein each processing layer has at least one processing unit and a plurality of memories, each of said processing units and memories being in communication with one another and wherein the total memory capacity of the chip is divided substantially equally between each of said processing layers.
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19. A processor for the processing of data based upon instructions, comprising:
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a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another; and a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to the processing layers. - View Dependent Claims (20, 21, 22)
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Specification