NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME
First Claim
1. A nanotube memory array comprising:
- a substrate;
a first conductor layer disposed on the substrate, the first conductor layer having a defined pattern;
a nanotube fabric layer disposed over and in electrical communication with the first conductor layer;
a second conductor layer disposed over, and in electrical communication with the nanotube fabric layer;
a memory operation circuit including a circuit for generating and applying a select signal on the first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers;
wherein at least two adjacent memory cells are formed in at least two selected cross sections of the first conductor layer, nanotube fabric layer, and second conductor layer, each memory cell uniquely addressable and programmable by said memory operation circuit, wherein for each memory cell, a change in the resistance between first and second conductor layers corresponds to a change in an informational state of the memory cell.
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Accused Products
Abstract
NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F2 memory cell density is achieved.
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Citations
57 Claims
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1. A nanotube memory array comprising:
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a substrate; a first conductor layer disposed on the substrate, the first conductor layer having a defined pattern; a nanotube fabric layer disposed over and in electrical communication with the first conductor layer; a second conductor layer disposed over, and in electrical communication with the nanotube fabric layer; a memory operation circuit including a circuit for generating and applying a select signal on the first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers; wherein at least two adjacent memory cells are formed in at least two selected cross sections of the first conductor layer, nanotube fabric layer, and second conductor layer, each memory cell uniquely addressable and programmable by said memory operation circuit, wherein for each memory cell, a change in the resistance between first and second conductor layers corresponds to a change in an informational state of the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A memory array, comprising:
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a plurality of memory cells, each memory cell receiving a bit line, a word line, and a reference line, each memory cell having a first electrode in electrical communication with said bit line; a nanotube article electrically interposed between at least one first electrode and at least one reference line corresponding to the plurality of memory cells; and a memory operation circuit in electrical communication with the bit line, the word line, and the reference line of each cell to activate a selected cell; said operation circuit including circuitry to program an informational state in at least a portion of the nanotube article, the circuitry applying electrical stimulus to at least one of the bit line, word line, and reference line, in which said electrical stimulus changes the resistance of at least a portion of the nanotube article between the first electrode and reference line; wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A method of making a memory array comprising:
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providing a plurality of bit lines and word lines; providing a plurality of first electrodes, each first electrode in communication with a bit line and each corresponding to a memory cell; forming a nanotube fabric over and in electrical communication with the first electrodes, the nanotube fabric comprising a network of unaligned nanotubes; providing a reference article over and in electrical communication with the nanotube fabric; and providing a memory operation circuit in electrical communication with the bit line, the word line, and the reference article to activate one or more selected memory cells, said memory operation circuit including circuitry to program an informational state in at least a portion of the nanotube fabric by applying electrical stimulus to at least one of the bit line, word line, and reference article, in which said electrical stimulus changes the resistance of at least a portion of the nanotube fabric between the first electrode and reference article; wherein a relatively high resistance in said portion of the nanotube fabric corresponds to a first informational state of the memory cell in the array, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell in the array. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
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Specification