NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME

• US 20100001267A1
• Filed: 06/17/2009
• Published: 01/07/2010
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: DERDERIAN, Garo, MANNING, H.M., WARD, Jonathan W., RUECKES, Thomas, BERTIN, Claude L.
• Granted Patent: US 8,587,989 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F² memory cell density is achieved.

Claims

1. A nanotube memory array comprising:

a substrate;

a first conductor layer disposed on the substrate, the first conductor layer having a defined pattern;

a nanotube fabric layer disposed over and in electrical communication with the first conductor layer;

a second conductor layer disposed over, and in electrical communication with the nanotube fabric layer;

a memory operation circuit including a circuit for generating and applying a select signal on the first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers;

wherein at least two adjacent memory cells are formed in at least two selected cross sections of the first conductor layer, nanotube fabric layer, and second conductor layer, each memory cell uniquely addressable and programmable by said memory operation circuit, wherein for each memory cell, a change in the resistance between first and second conductor layers corresponds to a change in an informational state of the memory cell.

2. The nanotube memory array of claim 1, wherein the first conductor layer comprises a plurality of substantially parallel first conductive traces and the second conductor layer comprises a plurality of substantially parallel second conductive traces.

3. The nanotube memory array of claim 2, wherein the first conductive traces and the second conductive traces are orthogonally disposed with respect to one another.

4. The nanotube memory array of claim 2, wherein the first conductive traces and the second conductive traces are non-orthogonally disposed with respect to another.

5. The nanotube memory array of claim 2, wherein the nanotube fabric layer comprises a plurality of patterned nanotube blocks, each nanotube block interposed between and positioned at a corresponding intersection of one first conductive trace and one second conductive trace.

6. The nanotube memory array of claim 1, wherein the nanotube fabric layer and the second conductor layer are conformally disposed and have a corresponding defined pattern.

7. The nanotube memory array of claim 6, wherein the nanotube fabric layer and the second conductor layer form a conductor-on-nanotube trace.

8. The nanotube memory array of claim 6, wherein the nanotube fabric layer and the second conductor layer form a conductor-on-nanotube plane.

9. The nanotube memory array of claim 1, wherein the defined pattern of the first conductor layer comprises an array of discrete first electrodes.

10. The nanotube memory array of claim 9, wherein the memory operation circuit comprises select diodes, each discrete first electrode disposed over and in electrical communication with a select diode.

11. The nanotube memory array of claim 1, wherein the defined pattern of the first conductor layer comprises a plurality of traces.

12. The nanotube memory array of claim 1, wherein the change in resistance of the nanotube fabric layer comprises a change between a first resistance state and a second resistance state, the first resistance state being a substantially higher resistance than the second resistance state.

13. The nanotube memory array of claim 12, wherein the first resistance state comprises a first information state and the second resistance state comprises a second information state.

14. The nanotube memory array of claim 1, wherein for said at least two adjacent memory cells, a change of resistance in a first memory cell is substantially unaffected by a change of resistance in a second memory cell.

15. The nanotube memory array of claim 1, wherein the nanotube fabric layer comprises a plurality of unaligned nanotubes providing a plurality of conductive pathways through the nanotube fabric layer.

16. The nanotube memory array of claim 1, wherein the first conductor layer is partially embedded in the substrate

17. A memory array, comprising:

a plurality of memory cells, each memory cell receiving a bit line, a word line, and a reference line, each memory cell having a first electrode in electrical communication with said bit line;

a nanotube article electrically interposed between at least one first electrode and at least one reference line corresponding to the plurality of memory cells; and

a memory operation circuit in electrical communication with the bit line, the word line, and the reference line of each cell to activate a selected cell;

said operation circuit including circuitry to program an informational state in at least a portion of the nanotube article, the circuitry applying electrical stimulus to at least one of the bit line, word line, and reference line, in which said electrical stimulus changes the resistance of at least a portion of the nanotube article between the first electrode and reference line;

wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell.

18. The memory array of claim 17, wherein each of the bit line, word line and reference line comprise traces having a width defined as F and wherein the memory array has a density of 6F².

19. The memory array of claim 17, wherein each of the reference lines corresponding to the plurality of memory cells is substantially parallel to each of the word lines corresponding to the plurality of memory cells.

20. The memory array of claim 17, wherein each of the reference lines corresponding to the plurality of memory cells is substantially parallel to each of the bit lines corresponding to the plurality of memory cells.

21. The memory array of claim 17, wherein each of the bit lines corresponding to the plurality of memory arrays is substantially orthogonal to each of the word lines corresponding to the plurality of memory cells.

22. The memory array of claim 17, wherein each of the bit lines corresponding to the plurality of memory arrays is positioned at a substantially non-orthogonal angle with respect to each of the word lines corresponding to the plurality of memory cells.

23. The memory array of claim 22, wherein the selected angle is approximately 76 degrees.

24. The memory array of claim 17, wherein the nanotube article comprises a plurality of nanotube blocks, each block corresponding to a memory cell, each block programmable with said informational state.

25. The memory array of claim 17, wherein the nanotube article comprises a plurality of nanotube traces and wherein each reference line is substantially conformally disposed over and aligned with a corresponding nanotube trace.

26. The memory array of claim 25, wherein a region of each nanotube trace corresponds to a memory cell, the region programmable with said informational state.

27. The memory array of claim 17, wherein the nanotube article comprises a nanotube plane disposed over the word lines and the bit lines corresponding to the plurality of memory cells.

28. The memory array of claim 27, wherein each reference line comprises a trace conformally disposed over a portion of the nanotube plane and wherein each of a plurality of regions of the nanotube plane corresponding to the plurality of memory cells is programmable with said information state.

29. The memory array of claim 27, wherein the reference line comprises a conductor plane disposed over and conformally to the nanotube plane, and wherein a plurality of regions of the nanotube plane corresponding to the plurality of memory cells is each programmable with said information state.

30. The memory array of claim 29, wherein for each memory cell, the region is the portion of the nanotube plane disposed over said corresponding first electrode.

31. The array of claim 17, wherein the first and second informational states are nonvolatile.

32. The array of claim 17, wherein the resistance of the relatively high resistance state is several times greater than the relatively low resistance state.

33. The array of claim 17, further comprising a cell selection circuit for each memory cell, the cell selection circuit electrically interposed between the first electrode and the bit line.

34. The array of claim 17, wherein the cell selection circuit includes a transistor with a gate, a source, and a drain, and wherein the gate is in electrical contact with the first word line, the source is in electrical contact with the first electrode, and the drain is in electrical contact with the bit line.

35. The array of claim 17, wherein said operation circuit reads an informational state of the memory cell by activating one of the bit line and the word line and applying a read stimulus to the bit line.

36. The array of claim 17, wherein the first electrode comprise at least one of metallic carbon nanotubes, Ti, TiN, Al, Ta, TaN, Cu, Ru, RuO, Pd, Co, CoSi_x, Ni, NiSi_x, TiSi_x, Si, Pt, PtSi_x, Au, Ag, and combinations thereof.

37. The array of claim 17, wherein an intermediate resistance of the nanotube article corresponds to a third informational state of the memory cell.

38. The array of claim 17, wherein the nanotube article is disposed over the bit lines.

39. The array of claim 17, wherein the bit lines are disposed over the nanotube article.

40. A method of making a memory array comprising:

providing a plurality of bit lines and word lines;

providing a plurality of first electrodes, each first electrode in communication with a bit line and each corresponding to a memory cell;

forming a nanotube fabric over and in electrical communication with the first electrodes, the nanotube fabric comprising a network of unaligned nanotubes;

providing a reference article over and in electrical communication with the nanotube fabric; and

providing a memory operation circuit in electrical communication with the bit line, the word line, and the reference article to activate one or more selected memory cells, said memory operation circuit including circuitry to program an informational state in at least a portion of the nanotube fabric by applying electrical stimulus to at least one of the bit line, word line, and reference article, in which said electrical stimulus changes the resistance of at least a portion of the nanotube fabric between the first electrode and reference article;

wherein a relatively high resistance in said portion of the nanotube fabric corresponds to a first informational state of the memory cell in the array, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell in the array.

41. The method of claim 40, wherein each bit line and each word line is patterned to have a width of F and wherein the memory array has a density of 6F².

42. The method of claim 40, wherein a selected portion of the memory array is active and a selected portion of the memory array is inactive.

43. The method of claim 42, wherein the inactive portion of the memory array includes memory cells in which an informational state is not programmed into corresponding portions of the nanotube fabric.

44. The method of claim 40, wherein the patterned reference article comprises a plurality of reference lines, the reference lines substantially parallel to either the bit lines or the word lines.

45. The method of claim 40, wherein the patterned reference article comprises a reference electrode plane carrying a single reference voltage.

46. The method of claim 40, further comprising patterning the nanotube fabric and the reference article to form conductor-on-nanotube traces.

47. The method of claim 46, wherein the conductor-on-nanotube traces are substantially parallel to either the bit lines or the word lines.

48. The method of claim 40, further comprising patterning the nanotube fabric into a plurality of nanotube blocks, each nanotube block corresponding to a memory cell.

49. The method of claim 40, further comprising embedding the first electrodes and the nanotube fabric in an insulating substrate.

50. The method of claim 40, wherein providing a plurality of first electrodes comprises forming a plurality of semiconductor devices, the first electrodes being one node of the semiconductor devices.

51. The method of claim 50, wherein the semiconductor devices are MOS access devices.

52. The method of claim 50, wherein the semiconductor devices are select diodes.

53. The method of claim 40, wherein the nanotube fabric is disposed over the bit lines.

54. The method of claim 40, wherein the bit lines are disposed over the nanotube fabric.

55. The method of claim 40, wherein a protective material is applied over an external surface of the nanotube fabric to protect the nanotube fabric during one or more fabrication steps, the protective material comprising at least one of silicon dioxide, silicon nitride, hafnium oxide, zirconium oxide, and aluminum oxide, amorphous silicon, W, Al, Ti, TiN, Ta, spin-on-glasses (SOGs), thermally decomposed polymers, and photoresists.

56. The method of claim 40, wherein forming the nanotube fabric further comprises forming a nanoparticle layer, the nanoparticle layer selected to adjust the resistance of at least a portion of the nanotube fabric between the first electrode and reference article.

57. The method of claim 56, wherein the nanoparticle layer comprises at least one of amorphous carbon, alumina, bismuth, cadmium, selenide, gallium nitride, gold, gallium phosphide, germanium, silicon, indium phosphide, magnesium oxide, manganese oxide, nickel, palladium, silicon carbide, titanium, zinc oxide, and silicon germanium.