TFT FLOATING GATE MEMORY CELL STRUCTURES
First Claim
1. A method of making a TFT floating gate memory cell structure, the method comprising:
- providing a substrate;
forming a first insulation layer on the substrate;
forming one or more source or drain regions on the first insulation layer, each of the one or more source or drain regions being associated with a first surface and including an N+ polysilicon layer, a barrier layer, and a conductive layer, the N+ polysilicon layer being on the barrier layer, the barrier layer overlying the conductive layer, the first surface consisting of N+ polysilicon;
forming a second insulation layer on the first insulation layer, the second insulation layer being associated with a second surface, the second surface being substantially co-planar with the first surface;
forming a P−
polysilicon layer overlying the first surface and the second surface, the P−
polysilicon layer being capable of forming a channel from the source region to the drain region;
forming a silicon layer sandwiched by an upper silicon dioxide block layer and a bottom silicon dioxide tunnel layer on the P−
polysilicon layer, the silicon layer being capable of forming a floating gate;
forming a P+ polysilicon layer on the upper silicon dioxide block layer; and
forming at least one control gate by patterning the P+ polysilicon layer.
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Accused Products
Abstract
A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
224 Citations
27 Claims
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1. A method of making a TFT floating gate memory cell structure, the method comprising:
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providing a substrate; forming a first insulation layer on the substrate; forming one or more source or drain regions on the first insulation layer, each of the one or more source or drain regions being associated with a first surface and including an N+ polysilicon layer, a barrier layer, and a conductive layer, the N+ polysilicon layer being on the barrier layer, the barrier layer overlying the conductive layer, the first surface consisting of N+ polysilicon; forming a second insulation layer on the first insulation layer, the second insulation layer being associated with a second surface, the second surface being substantially co-planar with the first surface; forming a P−
polysilicon layer overlying the first surface and the second surface, the P−
polysilicon layer being capable of forming a channel from the source region to the drain region;forming a silicon layer sandwiched by an upper silicon dioxide block layer and a bottom silicon dioxide tunnel layer on the P−
polysilicon layer, the silicon layer being capable of forming a floating gate;forming a P+ polysilicon layer on the upper silicon dioxide block layer; and forming at least one control gate by patterning the P+ polysilicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A device with thin-film transistor (TFT) floating gate memory cell structure, the device comprising:
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a substrate; a dielectric layer on the substrate, the dielectric layer being associated with a first surface; one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions including an N+ polysilicon layer, a diffusion barrier layer, and a first conductive layer, the N+ polysilicon layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the first conductive layer, the N−
polysilicon layer having a second surface substantially co-planar with the first surface;a P−
polysilicon layer overlying the first surface and the second surface;a silicon layer on the P−
polysilicon layer, the silicon layer being sandwiched by an upper oxide block layer and a bottom oxide tunnel layer;a second conductive layer overlying the upper oxide block layer; and at least one control gate made from patterning the second conductive layer. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification