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TFT FLOATING GATE MEMORY CELL STRUCTURES

  • US 20100001282A1
  • Filed: 10/27/2008
  • Published: 01/07/2010
  • Est. Priority Date: 07/03/2008
  • Status: Active Grant
First Claim
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1. A method of making a TFT floating gate memory cell structure, the method comprising:

  • providing a substrate;

    forming a first insulation layer on the substrate;

    forming one or more source or drain regions on the first insulation layer, each of the one or more source or drain regions being associated with a first surface and including an N+ polysilicon layer, a barrier layer, and a conductive layer, the N+ polysilicon layer being on the barrier layer, the barrier layer overlying the conductive layer, the first surface consisting of N+ polysilicon;

    forming a second insulation layer on the first insulation layer, the second insulation layer being associated with a second surface, the second surface being substantially co-planar with the first surface;

    forming a P

    polysilicon layer overlying the first surface and the second surface, the P

    polysilicon layer being capable of forming a channel from the source region to the drain region;

    forming a silicon layer sandwiched by an upper silicon dioxide block layer and a bottom silicon dioxide tunnel layer on the P

    polysilicon layer, the silicon layer being capable of forming a floating gate;

    forming a P+ polysilicon layer on the upper silicon dioxide block layer; and

    forming at least one control gate by patterning the P+ polysilicon layer.

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