SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

• US 20100001344A1
• Filed: 01/10/2007
• Published: 01/07/2010
• Est. Priority Date: 01/10/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Reynes, Jean-Michel, Deram, Ivana, Stefanov, Evgueniy
• Granted Patent: US 7,955,929 B2
• Time in Patent Office: Days
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Claims

1. A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprising:

providing a semiconductor substrate;

providing a semiconductor layer of a first conductivity type over the semiconductor substrate;

forming a mask layer over the semiconductor layer, the mask layer outlining at least three portions of a surface of the semiconductor layer, a first outlined portion outlining a floating region in the active area, a second outlined portion outlining a first termination region in the termination area and a third outlined portion outlining a second termination region in the termination area; and

providing dopant of a second conductivity type to the first, second and third outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and first and second termination regions of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device;

wherein a distance between the second outlined portion and the third outlined portion is less than a lateral spread of the dopant through the semiconductor layer such that the step of providing dopant to the second and third outlined portions provides a merged termination region in the termination area.

2. The method according to claim 1 wherein the doping concentration of the semiconductor material in the floating region is greater than the doping concentration of the semiconductor material in the first termination region.

3. The method according to claim 1, wherein the first outlined portion has a first width and the second outlined portion has a second width and wherein the first width is greater than the second width.

4. The method according to claim 1, wherein the forming a mask layer step comprises forming a mask layer over the semiconductor layer having at least three openings, a first opening corresponding to the first outlined portion and second and third openings corresponding to the second and third outlined portions, and wherein the providing dopant step comprises providing the dopant through the first, second and third openings into the semiconductor layer.

5. The method according to claim 3, wherein the third outlined portion has a third width, the third width being substantially the same as the second width.

6. The method according to claim 3, wherein the first termination region is located in the semiconductor layer between the floating region and the second termination region, wherein the third outlined portion has a third width, the third width being less than the second width such that the doping concentration of the semiconductor material in the first termination region is greater than the doping concentration of the semiconductor material in the second termination region.

7. The method according to claim 1, wherein the step of providing dopant includes the step of driving the dopant into the semiconductor layer so as to form the floating region and the first and second termination regions buried in the semiconductor layer.

8. The method according to claim 1, further comprising:

forming a field plate extending across a portion of the semiconductor layer in the termination area adjacent the active area; and

forming at least one termination region buried in the semiconductor layer in the termination area, the at least one termination region extending to a distance from an edge of the field plate.

9. The method according to claim 1, wherein a plurality of termination regions are formed buried in the semiconductor layer in the termination area and wherein a distance between an outlined portion of the mask layer outlining a termination region and an outlined portion outlining an adjacent termination region varies away from the active area.

10. The method according to claim 1, wherein a plurality of termination regions are formed buried in the semiconductor layer in the termination area and wherein the doping concentration of the dopant in the plurality of termination regions varies away from the active area.

11. The method according to claim 1, wherein a plurality of termination regions are formed buried in the semiconductor layer in the termination area and wherein the method further comprises the step of forming enhancement regions of the first conductivity type buried in the semiconductor layer between the termination regions.

12. The method according to claim 1, wherein a plurality of floating regions are formed buried in the semiconductor layer in the active area and wherein the method further comprises the step of forming enhancement regions of the first conductivity type buried in the semiconductor layer between the floating regions.

13. The method according to claim 1, wherein a shape of the second outlined portion of the mask layer defines a shape of the first termination region, the shape of the first termination region being one of stripe, dot, mesh shape, and cross-shape.

14. The method according to claim 1, wherein the semiconductor device comprises any one of the following devices:

MOSFET, IGBT, JFET, diode.

15. A semiconductor device formed according to the method of claim 1.

16. The method according to claim 2, wherein the first outlined portion has a first width and the second outlined portion has a second width and wherein the first width is greater than the second width.

17. The method according to claim 2, wherein the forming a mask layer step comprises forming a mask layer over the semiconductor layer having at least three openings, a first opening corresponding to the first outlined portion and second and third openings corresponding to the second and third outlined portions, and wherein the providing dopant step comprises providing the dopant through the first, second and third openings into the semiconductor layer.

18. The method according to claim 2, further comprising:

forming a field plate extending across a portion of the semiconductor layer in the termination area adjacent the active area; and

forming at least one termination region buried in the semiconductor layer in the termination area, the at least one termination region extending to a distance from an edge of the field plate.

19. The method according to claim 10, wherein a plurality of floating regions are formed buried in the semiconductor layer in the active area and wherein the method further comprises the step of forming enhancement regions of the first conductivity type buried in the semiconductor layer between the floating regions.

20. The method according to claim 8, wherein a plurality of floating regions are formed buried in the semiconductor layer in the active area and wherein the method further comprises the step of forming enhancement regions of the first conductivity type buried in the semiconductor layer between the floating regions.