Treatment of Gate Dielectric for Making High Performance Metal Oxide and Metal Oxynitride Thin Film Transistors
First Claim
1. A thin film transistor fabrication method, comprising:
- depositing a gate dielectric layer over a gate electrode and a substrate;
exposing the gate dielectric layer to an oxygen containing plasma;
depositing a semiconductor layer over the gate dielectric layer, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, tin, and combinations thereof;
depositing a conductive layer over the semiconductor layer; and
etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer.
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Abstract
Embodiments of the present invention generally include TFTs and methods for their manufacture. The gate dielectric layer in the TFT may affect the threshold voltage of the TFT. By treating the gate dielectric layer prior to depositing the active channel material, the threshold voltage may be improved. One method of treating the gate dielectric involves exposing the gate dielectric layer to N2O gas. Another method of treating the gate dielectric involves exposing the gate dielectric layer to N2O plasma. Silicon oxide, while not practical as a gate dielectric for silicon based TFTs, may also improve the threshold voltage when used in metal oxide TFTs. By treating the gate dielectric and/or using silicon oxide, the threshold voltage of TFTs may be improved.
117 Citations
20 Claims
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1. A thin film transistor fabrication method, comprising:
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depositing a gate dielectric layer over a gate electrode and a substrate; exposing the gate dielectric layer to an oxygen containing plasma; depositing a semiconductor layer over the gate dielectric layer, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, tin, and combinations thereof; depositing a conductive layer over the semiconductor layer; and etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A thin film transistor fabrication method, comprising:
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depositing a silicon nitride layer over a gate electrode and a substrate; depositing a silicon oxide layer over the silicon nitride layer; depositing a semiconductor layer over the silicon oxide layer, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, tin, and combinations thereof; depositing a conductive layer over the semiconductor layer; and etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A thin film transistor fabrication method, comprising:
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depositing a silicon oxide layer over a gate electrode and a substrate; depositing a semiconductor layer over the silicon oxide layer, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, tin, and combinations thereof; depositing a conductive layer over the semiconductor layer; and etching the conductive layer to define source and drain electrodes and an active channel, the active channel exposing a portion of the semiconductor layer. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A thin film transistor, comprising:
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a silicon oxide layer disposed over a gate electrode and a substrate; a semiconductor layer disposed over the silicon oxide layer, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, tin, and combinations thereof; and a source electrode and a drain electrode disposed over the semiconductor layer, the source and drain electrodes spaced from each other to expose a portion of the semiconductor layer. - View Dependent Claims (20)
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Specification