TRIPLE WELL TRANSMIT-RECEIVE SWITCH TRANSISTOR

• US 20100001351A1
• Filed: 09/21/2006
• Published: 01/07/2010
• Est. Priority Date: 09/21/2006
• Status: Active Grant

• Current Assignee: Nanyang Technology University
• Original Assignee: Nanyang Technology University
• Inventors: Li, Qiang, Zhang, Yue Ping
• Granted Patent: US 8,288,829 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.

Claims

1. A transistor arrangement comprising a triple well structure, the triple well structure comprising

a substrate of a first conductivity type;

a first well region of a second conductivity type formed within the substrate;

a second well region of the first conductivity type being separated from the substrate by the first well region;

a first transistor formed on or in the second well region, the first transistor comprising a body terminal being connected to the second well region; and

a second well region switch being connected to the body terminal of the first transistor

wherein the body terminal of the first transistor is connected to a reference potential when the second well region switch is closed.

2. The transistor arrangement of claim 1, further comprising

a controller being connected to a control terminal of the second well region switch and controlling the second well region switch to be opened when the first transistor is in the ON state and to be closed when the first transistor is in the OFF state.

3. The transistor arrangement of claim 1, the substrate being a P-type substrate.

4. The transistor arrangement of claim 3, the first well region being an N-type well region.

5. The transistor arrangement of claim 4, the second well region being a P-type well region.

6. The transistor arrangement of claim 1, the first transistor further comprising a source terminal, a gate terminal and a drain terminal.

7. The transistor arrangement of claim 6, the source terminal comprising a source diffusion region of the second conductivity type being formed in the second well region;

the drain terminal comprising a drain diffusion region of the second conductivity type being formed in the second well region.

8. The transistor arrangement of claim 1, the body terminal comprising a body diffusion region of the first conductivity type being formed in the second well region.

9. The transistor arrangement of claim 1, the second well region switch being a second transistor.

10. The transistor arrangement of claim 9, the second transistor being a field-effect transistor or a bipolar transistor.

11. The transistor arrangement of claim 9, the second transistor being selected from a group of transistors consisting of metal-oxide-semiconductor field-effect transistor, n-channel metal-oxide-semiconductor field-effect transistor, p-channel metal-oxide-semiconductor field-effect transistor, junction gate field-effect transistor, insulated gate bipolar transistor.

12. The transistor arrangement of claim 1, further comprising a first well region terminal connected to the first well region.

13. The transistor arrangement of claim 12, the first well region terminal connected to the first well region comprising a diffusion region of the second conductivity type being formed in the first well region.

14. The transistor arrangement of claim 12, further comprising a passive component being coupled to the first well region terminal.

15. The transistor arrangement of claim 14, the passive component comprising a component selected from the group consisting of resistor, inductor and capacitor.

16. The transistor arrangement of claim 12, a first well region switch being coupled to the first well region terminal.

17. The transistor arrangement of claim 16, the first well region switch being a third transistor.

18. The transistor arrangement of claim 17, the third transistor being a field-effect transistor or a bipolar transistor.

19. The transistor arrangement of claim 17,

the third transistor being selected from a group of transistors consisting of metal-oxide-semiconductor field-effect transistor, n-channel metal-oxide-semiconductor field-effect transistor, p-channel metal-oxide-semiconductor field-effect transistor, junction gate field-effect transistor, insulated gate bipolar transistor.

20. The transistor arrangement of claim 1, having a single-ended architecture.

21. The transistor arrangement of claim 1, having a differential architecture.

22. The transistor arrangement of claim 1, a fourth transistor having a source terminal, a gate terminal and a drain terminal.

23. The transistor arrangement of claim 22, the gate terminal of the first transistor and the gate terminal of the fourth transistor being arranged at a distance from one another of at least about twice the maximum process technology resolution.

24. (canceled)

25. (canceled)