SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

• US 20100001409A1
• Filed: 10/29/2007
• Published: 01/07/2010
• Est. Priority Date: 11/09/2006
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Humbert, Aurelie, Hoofman, Romano
• Application Number:
  US12/514,214
• Publication Number:
  US 20100001409A1
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

The invention relates to a semiconductor device comprising: a substrate (1), the substrate (1) comprising a body (5), the body (5) having a surface, the substrate (1) being provided with an insulating layer (10) on the surface of the body (1);—a conductor (25) with insulating sidewall spacers (22) located in the insulating layer (10), the conductor (25) having a current-flow direction during operation, the conductor (25) having a first width, the insulating sidewall spacers (22) each having a second width being smaller than the first width of the conductor (25), the first width and the second width being measured in a direction perpendicular to the current-flow direction of the conductor (25) and parallel to said surface, the conductor (25) having a first top surface extending parallel to said surface, the insulating sidewall spacers (22) having a second top surface, and airgaps (30) located in the insulating layer (10) adjacent to the insulating sidewall spacers (22), characterized in that the first top surface coincides with the second top surface, and in that the airgaps (30) extend from the surface of the body (5) to said first and second top surface. The invention further relates to a method of manufacturing such a semiconductor device. The semiconductor device according to the invention enables a lower resistance of the conductor while still providing a tolerance for unlanded vias.

Claims

1. A semiconductor device comprising:

a substrate, the substrate comprising a body, the body having a surface, the substrate being provided with an insulating layer on the surface of the body;

a conductor with insulating sidewall spacers located in the insulating layer, the conductor having a current-flow direction during operation, the conductor having a first width, the insulating sidewall spacers each having a second width being smaller than the first width of the conductor, the first width and the second width being measured in a direction perpendicular to the current-flow direction of the conductor and parallel to said surface, the conductor having a first top surface extending parallel to said surface, the insulating sidewall spacers having a second top surface, and

airgaps located in the insulating layer adjacent to the insulating sidewall spacers,

characterized in that the first top surface coincides with the second top surface, and in that the airgaps extend from the surface of the body to said first and second top surface.

2. A semiconductor device as claimed in claim 1, characterized in that the substrate further comprises a further insulating layer being provided on top of the insulating layer, the further insulating layer being provided with a further opening, the further opening being filled with a further conductor, wherein at least one part of the further conductor lands on the first top surface of the conductors.

3. A semiconductor device according to claim 1, characterized in that the width of the insulating sidewall spacers lies between 5% and 40% of the width of the conductor.

4. A method of manufacturing a semiconductor device comprising steps of:

providing a substrate, the substrate comprising a body, the body having a surface, the substrate being provided with an insulating layer on the surface of the body;

forming a conductor with insulating sidewall spacers in the insulating layer, the conductor having a current-flow direction during operation, the conductor having a first width, the insulating sidewall spacers each having a second width being smaller than the first width of the conductor, the first width and the second width being measured in a direction perpendicular to the current-flow direction of the conductor and parallel to said surface, the conductor having a first top surface extending parallel to said surface, the insulating sidewall spacers having a second top surface, the first top surface coinciding with the second top surface, and

forming airgaps in the insulating layer adjacent to the insulating sidewall spacers, the airgaps extending from the surface of the body to said first and second top surface.

5. A method as claimed in claim 4, characterized in that, in the step of providing the substrate, the insulating layer has been provided with an opening having sidewalls, the opening having a third width, the third width being measured in the direction parallel to said surface, and in that the conductor is provided in the openings.

6. A method as claimed in claim 5, characterized in that the step of forming the conductor with insulating sidewall spacers, comprises:

a first sub-step in which the insulating sidewall spacers are formed on the sidewalls of the opening, the second width of the insulating sidewall spacers being smaller than one third of the third width of the opening; and

a second sub-step in which the conductor is formed in the opening between the insulating sidewall spacers.

7. A method as claimed in claim 6, characterized in that, in the step of providing the substrate, at least parts of the insulating layer, located adjacent to the opening, have been provided as sacrificial regions, and in that the airgaps are formed by removing the sacrificial regions after that the insulating sidewall spacers and the conductor have been formed.

8. A method as claimed in claim 7, characterized in that the sacrificial regions have been formed by local damaging of material of the insulating layer.

9. A method as claimed in claim 8, characterized in that the step of locally damaging of material of the insulating layer takes place during formation of the opening by means of etching.

10. A method as claimed in claim 5, characterized in that, in the step of providing the substrate, parts of the insulating layer, located at a predefined distance from the opening, have been provided as sacrificial regions which define insulating regions between the conductor and the sacrificial regions, the predefined distance being smaller than the first width of the conductor, wherein the insulating sidewall spacers are defined by the insulating regions, and in that the airgaps are formed by removing the sacrificial regions which further forms the insulating sidewall spacers.

11. A method as claimed in claim 10, characterized in that the sacrificial regions are formed by local damaging of material of the insulating layer by means of ion bombardment.

12. A method as claimed in claim 4, characterized in that the insulating layer is fully provided as sacrificial region.

13. A method as claimed in claim 4, characterized in that the semiconductor device is provided with a further insulating layer, the further insulating layer being provided with a further opening, the further opening being filled with a further conductor, wherein at least one part of the further conductor lands on the first top surface of the conductor.

14. A method as claimed in claim 13, characterized in that at least a top part of the further conductor is provided with further spacers.

15. A method according to claim 4, characterized in that the insulating sidewall spacers are provided with a width that lies between 5% and 40% of the width of the conductor.