DUAL SENSITIVITY IMAGE SENSOR

• US 20100002118A1
• Filed: 09/11/2009
• Published: 01/07/2010
• Est. Priority Date: 06/15/1999
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Barna, Sandor, Wang, Yibing (Michelle)
• Granted Patent: US 7,889,258 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/585 with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.

Claims

1-32. -32. (canceled)

33. A dual sensitivity pixel comprising:

first and second photosensors, the first photosensor being of a higher light sensitivity than the second photosensor;

a transfer gate positioned between the first and second photosensors; and

readout circuitry connected to the second photosensor operable to produce output signals corresponding to charge produced by each of the first and second photosensors during respective first and second overlapping integration periods,

wherein the first photosensor is readout by sampling charge stored in the second photosensor after the transfer gate positioned between the first and second photosensors is activated to cause charge produced by the first photosensor to be transferred to the second photosensor.

34. The dual sensitivity pixel of claim 33, wherein the second photosensor is configured as a floating diffusion region.

35. The dual sensitivity pixel of claim 33, further including a reset transistor, connected between a reset voltage terminal and the second photosensor.

36. The dual sensitivity pixel of claim 35, wherein the readout circuitry is operable to:

reset the second photosensor to a reset level,

sample the reset level,

allow the second integration period to elapse, and

sample a pixel image signal level from the second photosensor,

before the transfer gate is activated to cause charge from the first photosensor to be transferred to the second photosensor.

37. The dual sensitivity pixel of claim 33, wherein the readout circuitry comprises separate sample and hold circuitry for sampling each of a pixel reset level and pixel image signal levels from the first and second photosensors.

38. The dual sensitivity pixel of claim 37, wherein the readout circuitry is configured to output a first, low sensitivity output indicative of a difference between the pixel image signal level from the second photosensor and the pixel reset level and a second, high sensitivity output indicative of a difference between the pixel image signal level from the first photosensor and the pixel reset level.

39. The dual sensitivity pixel of claim 33, wherein the first and second integration period overlap for at least 80% of a common integration period.

40. An image sensor comprising:

A plurality of pixels arranged in rows and columns, at least one of the pixels comprising;

high and low sensitivity photosensors for outputting a high and low sensitivity signals, respectively, wherein said high sensitivity signal is obtained by integration of the high sensitivity photosensor over a first integration period, and said low sensitivity signal is obtained by integration of the low sensitivity photosensor over a second integration period; and

readout circuitry connected to the low sensitivity photosensor,

wherein said high sensitivity photosensor is connected to the low sensitivity photosensor such that the high sensitivity signal can be sampled by the readout circuitry by transfer to and subsequent sampling of the low sensitivity photosensor after said low sensitivity signal has been sampled.

41. The image sensor of claim 40, wherein the low sensitivity photosensor is a floating diffusion region.

42. The image sensor of claim 40, wherein the pixel further comprises a reset transistor connected to the low sensitivity photosensor, and the readout circuitry is further adapted to sample a reset signal from the low sensitivity photosensor after the reset transistor is activated.

43. The image sensor of claim 40, wherein the readout circuitry comprises separate sample and hold circuitry for sampling each of a reset signal and pixel signal levels from both the high and low sensitivity photosensors.

44. The image sensor of claim 40, wherein the high and low sensitivity photosensors are operable to be integrated for first and second overlapping integrations periods, respectively.

45. The image sensor of claim 44, wherein the first integration period is longer than the second integration period.

46. The image sensor of claim 45, wherein the first and second integration periods overlap for at least 80% of a common integration period.

47. The image sensor of claim 40, wherein the high sensitivity photosensor is about 30-40 times more sensitive to light than the low sensitivity photosensor.

48. An image processor, comprising

a processor;

and

an imager, comprising;

a pixel array arranged in rows and columns, at least one pixel in the array comprising;

high and low sensitivity photosensors;

a transfer gate positioned between the high and low sensitivity photosensors; and

readout circuitry connected to the low sensitivity photosensor operable to produce output signals corresponding to charge produced by each of the high and low sensitivity photosensors during respective first and second overlapping integration periods,

wherein the high sensitivity photosensor is readout by sampling charge stored in the low sensitivity photosensor after the transfer gate positioned between the high and low sensitivity photosensors is activated to cause charge produced by the high sensitivity photosensor to be transferred to the low sensitivity photosensor.

49. The image processor of claim 48, wherein the low sensitivity photosensor is configured as a floating diffusion region.

50. The image processor of claim 48, wherein the high sensitivity photosensor is about 30-40 times more sensitive to light than the low sensitivity photosensor.

52. The image processor of claim 48, wherein the readout circuitry comprises separate sample and hold circuitry for sampling each of a pixel reset level and pixel image signal levels from the high and low sensitivity photosensors.

52-1. The image processor of claim 48, further comprising a control circuit, operating to control said first and second integration periods such that the first integration period is at least as long as the second integration period and the overlap between the two periods is at least 80%.