CIRCUIT BOARD HAVING SEMICONDUCTOR CHIP EMBEDDED THEREIN

• US 20100002406A1
• Filed: 07/01/2009
• Published: 01/07/2010
• Est. Priority Date: 07/04/2008
• Status: Abandoned Application

• Current Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Original Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Inventors: Hsu, Shin-Ping
• Application Number:
  US12/496,136
• Publication Number:
  US 20100002406A1
• Time in Patent Office: Days
• US Class Current: 361/764
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/2413 Connecting within a semiconductor or solid-state body
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0376 : Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/465 : by applying an insulating layer having channels for the next circuit layer

Abstract

A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.

Claims

1. A circuit board having a semiconductor chip embedded therein, comprising:

a core board having opposing first and second surfaces and a through-hole penetrating the first and second surfaces;

a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein a plurality of first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface;

a first dielectric layer disposed on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as for the semiconductor chip to be fixed in position to the through-hole; and

a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with a plurality of first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads provided on the semiconductor chip, wherein the first circuit layer has a plurality of series-connection portions.

2. The circuit board of claim 1, wherein the core board is an insulated board.

3. The circuit board of claim 2, wherein the second active surface of the semiconductor chip is an inactive surface.

4. The circuit board of claim 1, wherein a passivation layer is disposed on the first active surface of the semiconductor chip, allowing the first electrode pads to be provided on the passivation layer and electrically connected to the semiconductor chip.

5. The circuit board of claim 1, further comprising an alignment target disposed in a clean area of the semiconductor chip or being one of the first electrode pads.

6. The circuit board of claim 1, wherein the first dielectric layer has a plurality of first vias and first trenches, and portions of the first trenches are in communication with the first vias, allowing the first circuit layer to be disposed in the first trenches and the first conductive vias in the first vias.

7. The circuit board of claim 1, wherein the series-connection portions are electrically connected to at least two said power pads.

8. The circuit board of claim 1, wherein the series-connection portions are electrically connected to at least two said ground pads.

9. The circuit board of claim 1, further comprising a first build-up structure disposed on the first dielectric layer and the first circuit layer, the first build-up structure comprising:

a second dielectric layer having second vias and second trenches, a second circuit layer disposed in the second trenches of the second dielectric layer and flush with the second dielectric layer, and a plurality of second conductive vias disposed in the second vias of the second dielectric layer, allowing the second conductive vias to be electrically connected to the first and second circuit layers, the second circuit layer on top of the first build-up structure to be provided with the first electrical contact pads, the first build-up structure to be covered with a first solder mask layer, and a portion of a surface of the first electrical contact pads to be exposed from a plurality of first solder mask layer openings in the first solder mask layer.

10. The circuit board of claim 1, wherein the core board is configured to be a circuit board having circuits thereon, provided with a core circuit layer on the first surface and the second surface of the core board, and provided with a plating through hole or fourth conductive vias penetrating the core board for electrically connecting the core circuit layer on the first and second surfaces of the core board.

11. The circuit board of claim 10, wherein the second active surface of the semiconductor chip is an inactive surface.

12. The circuit board of claim 11, further comprising a second solder mask layer disposed on the second surface of the core board and provided with a plurality of solder mask layer openings for exposing the inactive surface of the semiconductor chip.

13. The circuit board of claim 10, further comprising a second build-up structure provided on the second surface of the core board, the second build-up structure comprising:

a third dielectric layer having third vias and third trenches, a third circuit layer disposed in the third trenches of the third dielectric layer and flush with the third dielectric layer, and a plurality of third conductive vias disposed in the third vias of the third dielectric layer and electrically connected to the third circuit layer, wherein a plurality of second electrical contact pads are provided on the third circuit layer on top of the second build-up structure, and the second build-up structure is covered with a second solder mask layer having a plurality of second solder mask layer openings provided therein for exposing a portion of a surface of the second electrical contact pads.

14. The circuit board of claim 13, wherein the first dielectric layer and the third dielectric layer fill a gap between the through-hole of the core board and the semiconductor chip so as for the semiconductor chip to be fixed in position to the through-hole.

15. The circuit board of claim 1, wherein a plurality of second electrode pads are provided on the second active surface of the semiconductor chip.

16. The circuit board of claim 15, further comprising a second build-up structure provided on the second surface of the core board and the second active surface of the semiconductor chip, the second build-up structure comprising:

a third dielectric layer having third vias and third trenches, a third circuit layer disposed in the third trenches of the third dielectric layer and flush the third dielectric layer, and a plurality of third conductive vias disposed in the third vias of the third dielectric layer and electrically connected to the third circuit layer and second electrode pads, allowing the third circuit layer on top of the second build-up structure to be provided with a plurality of second electrical contact pads, the second build-up structure to be covered with a second solder mask layer, and a portion of a surface of the second electrical contact pads to be exposed from a plurality of second solder mask layer openings in the second solder mask layer.

17. The circuit board of claim 16, wherein the first dielectric layer and the third dielectric layer fill a gap between the through-hole of the core board and the semiconductor chip so as for the semiconductor chip to be fixed in position to the through-hole.