Mulitple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same

• US 20100002504A1
• Filed: 07/02/2008
• Published: 01/07/2010
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Petrie, William Francis
• Granted Patent: US 7,729,166 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M^th virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Claims

1. A multiple-bit per cell (MBC) non-volatile memory apparatus comprising:

a memory array including an electrically erasable block;

the block including a reprogrammable page;

the reprogrammable page comprising an upper and a lower page sharing a common word-line;

the upper and lower pages including respective upper and lower data fields;

the upper and lower data fields including respective virtual upper and lower cells of MBC memory cells;

the MBC memory cells having respective threshold voltages programmable to a selected one of first level, second level, third level, or fourth level in order from the lowest voltage level,

wherein programming the lower cells comprises programming the respective threshold voltages from the first threshold voltage level to the second threshold voltage level, and

programming upper cells comprises programming the respective threshold voltages from the first threshold voltage level to the fourth threshold voltage level or from the second threshold voltage level to the third threshold voltage level; and

a controller for writing data to the memory array, wherein the controller controls polarity by selectively inverting a data word to maximize a number of bits within a lower page to be programmed and selectively inverting a data to minimize a number of bits to be programmed in the respective upper page.

2. The apparatus as claimed in claim 1 wherein the upper and lower pages comprise respective upper and lower spare fields.

3. The apparatus as claimed in claim 2 wherein the upper and lower spare fields comprise respective upper and lower page polarity flags.

4. The apparatus as claimed in claim 1 wherein the first level, the second level, the third level, and the fourth level of threshold voltages are defined as ‘

11’

, ‘

10’

, ‘

00’

, and ‘

01’

combinations of the upper and lower cells each respectively.

5. The apparatus as claimed in claim 4 wherein the first level threshold voltage represents an erased state.

6. The apparatus as claimed in claim 4 wherein the first level threshold voltage represents an unprogrammed upper cell and an unprogrammed lower cell.

7. The apparatus as claimed in claim 1 wherein the second level threshold voltage represents an unprogrammed upper cell and a programmed lower cell.

8. The apparatus as claimed in claim 1 wherein the third level threshold voltage represents a programmed upper cell and a programmed lower cell.

9. The apparatus as claimed in claim 1 wherein the second level threshold voltage represents a programmed upper cell and a unprogrammed lower cell.

10. The apparatus as claimed in claim 1 wherein the upper and lower pages further comprise respective upper and lower spare fields.

11. The apparatus as claimed in claim 10 wherein the upper and lower spare fields include respective upper and lower polarity flags.

12. The apparatus as claimed in claim 1 wherein the controller comprises means for reading a data from the memory array wherein the controller includes means for reading a data word from a page, means for decoding the data word into lower and upper data words, means for inverting the lower data word if a lower page polarity flag is set, and means for inverting the upper data word if an upper page polarity flag is set.

13. A non-volatile memory (NVM) system comprising:

a multiple-bit per cell (MBC) non-volatile memory apparatus including;

a memory array including an electrically erasable block;

the blocks including a reprogrammable page;

the reprogrammable page comprising upper and lower pages sharing common word-lines;

the upper and lower pages including respective upper and lower data fields;

the upper and lower data fields including respective virtual upper and lower cells of MBC memory cells;

the MBC memory cells having respective threshold voltages programmable to a selected one of first level, second level, third level, or fourth level in order from the lowest voltage level,

wherein programming the lower cells comprises programming the respective threshold voltages from the first threshold voltage level to the second threshold voltage level, and

programming upper cells comprises programming the respective threshold voltages from the first threshold voltage level to the fourth threshold voltage level or from the second threshold voltage level to the third threshold voltage level; and

a controller for writing data to the memory array, wherein the controller controls polarity by selectively inverting data to maximize a number of the bits within a lower page to be programmed and selectively inverting data to minimize a number of bits to be programmed in the respective upper page.

14. The system as claimed in claim 13 wherein the upper and lower pages comprise respective upper and lower spare fields.

15. The system as claimed in claim 14 wherein the upper and lower spare fields comprise respective upper and lower page polarity flags.

16. The system as claimed in claim 13 wherein the first level, the second level, the third level, and the fourth level of threshold voltages are defined as ‘

11’

, ‘

10’

, ‘

00’

, and ‘

01’

combinations of the upper and lower cells each respectively.

17. The system as claimed in claim 16 wherein the first level threshold voltage represents an erased state.

18. The system as claimed in claim 16 wherein the first level threshold voltage represents an unprogrammed upper cell and an unprogrammed lower cell.

19. The system as claimed in claim 13 wherein the second level threshold voltage represents an unprogrammed upper cell and a programmed lower cell.

20. The system as claimed in claim 13 wherein the third level threshold voltage represents a programmed upper cell and a programmed lower cell.

21. The system as claimed in claim 13 wherein the second level threshold voltage represents a programmed upper cell and an unprogrammed lower cell.

22. The system as claimed in claim 13 wherein the upper and lower pages further comprise respective upper and lower spare fields.

23. The system as claimed in claim 22 wherein the upper and lower spare fields include respective upper and lower polarity flags.

24. The system as claimed in claim 13 wherein the controller comprises means for reading data from the memory array wherein the controller includes means for sensing threshold voltages of MBC cells within a page, means for providing an upper data word by comparing the threshold voltages to a predetermined voltage reference, and means for inverting the upper data word if a upper page polarity flag is set.

25. The system as claimed in claim 13 wherein the controller comprises means for reading data from the memory array wherein the controller includes means for sensing threshold voltages of MBC cells within a page, means for providing a lower data word by comparing the threshold voltages to two predetermined voltage references, and means for inverting the lower data word if a lower page polarity flag is set

26. A method of programming a lower page and an upper page in a multi-bit per cell (MBC) non-volatile memory, the method comprising steps of:

counting a number of bits having a ‘

0’

in a lower data word;

inverting all of the bits in the lower data word if the number of ‘

0’

bits is less than half of a total number of bits in the lower data word;

programming the lower page with the lower data word;

counting a number of bits having a ‘

0’

in an upper data word;

inverting all of the bits in the upper data word if the number of ‘

0’

bits is greater than half of a total number of bits in the upper data word; and

programming the upper page with the upper data word.

27. A method as claimed in claim 26 wherein the step of inverting all of the bits in the lower data word comprises a step of setting a lower page polarity flag.

28. A method as claimed in claim 26 wherein the step of inverting all of the bits in the upper data word comprises a step of setting an upper page polarity flag.

29. A method as claimed in claim 26 further comprising the step of clearing a lower page polarity flag.

30. A method as claimed in claim 26 further comprising the step of clearing an upper page polarity flag.

31. A method of reading data in a multi-bit per cell (MBC) non-volatile memory, the method comprising steps of:

sensing threshold voltages of MBC cells within a page;

providing an upper data word by comparing the threshold voltages to a predetermined voltage reference; and

inverting the upper data word if an upper page polarity flag is set.

32. A method as claimed in claim 31 wherein the step of inverting the upper data word comprises a step of reading the upper page polarity flag from a spare field.

33. A method of reading data in a multi-bit per cell (MBC) non-volatile memory, the method comprising steps of:

sensing threshold voltages of MBC cells within a page;

providing a lower data word by comparing the threshold voltages to two predetermined voltage references; and

inverting the lower data word if a lower page polarity flag is set.

34. A method as claimed in claim 33 wherein the step of inverting the lower data word comprises a step of reading the lower page polarity flag from a spare field.

35. A multiple-bit per cell (MBC) non-volatile memory apparatus comprising:

a memory array including an electrically erasable block;

the block including a reprogrammable page;

the reprogrammable page comprising M virtual pages sharing a common word-line;

the M virtual pages including respective data fields;

each of the data fields including a respective virtual cell of an M bit per cell MBC memory cell;

the MBC memory cell having a threshold voltage programmable to a selected one of N levels,

wherein N=2^M, and

wherein programming an m^th bit of the M bits of the MBC memory cell includes programming the MBC memory cell from one of states 1 . . . 2<sup>m−

1</sup> to one of states 2^m . . . 2<sup>m−

1</sup>+1 respectively; and

a controller for writing data to the memory array, wherein the controller controls polarity by selectively inverting a polarity of respective data words to be programmed into the 1^st to (M−

1)^th virtual pages to maximize a number of bits to be programmed within each of the respective (M−

1)^th virtual pages and selectively inverting a polarity of respective data words to be programmed into the M^th virtual page to minimize a number of bits to be programmed within M^th virtual page.

36. A method of reading data in an M-bit multi-bit per cell (MBC) non-volatile memory, the method comprising steps of:

sensing threshold voltages of MBC cells within a page;

comparing the threshold voltages to 2^M−

1 predetermined reference voltages;

providing a data word based on the comparisons; and

inverting the data word if a polarity flag is set.

37. A system including a multi-bit per cell (MBC) non-volatile memory including means for reading data comprising:

means for sensing threshold voltages of MBC cells within a page;

means for providing an upper data word by comparing the threshold voltages to a predetermined voltage reference; and

means for inverting the upper data word if an upper page polarity flag is set.

38. A system as claimed in claim 37 wherein the means for inverting the upper data word comprises means for reading the upper page polarity flag from a spare field.

39. A memory controller for reading data in a multi-bit per cell (MBC) non-volatile memory comprising:

means for sensing threshold voltages of MBC cells within a page;

means for providing an upper data word by comparing the threshold voltages to a predetermined voltage reference; and

means for inverting the upper data word if an upper page polarity flag is set.

40. A memory controller as claimed in claim 39 wherein the means for inverting the upper data word comprises means reading the upper page polarity flag from a spare field.

41. A memory controller for reading data in a multi-bit per cell (MBC) non-volatile memory comprising:

means for sensing threshold voltages of MBC cells within a page;

means for providing a lower data word by comparing the threshold voltages to two predetermined voltage references; and

means for inverting the lower data word if a lower page polarity flag is set.

42. A memory controller as claimed in claim 41 wherein the means for inverting the lower data word comprises means for reading the lower page polarity flag from a spare field.