DISABLING FAULTY FLASH MEMORY DIES

• US 20100002512A1
• Filed: 09/14/2009
• Published: 01/07/2010
• Est. Priority Date: 01/18/2006
• Status: Active Grant

• Current Assignee: Christopher P. Dudte, Michael J. Cornwell
• Original Assignee: Christopher P. Dudte, Michael J. Cornwell
• Inventors: Cornwell, Michael J., Dudte, Christopher P.
• Granted Patent: US 8,055,959 B2
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level.

Claims

1. An article of manufacture comprising machine-readable instructions that, when executed, cause operations to be performed, the operations comprising:

identifying at least one criterion for determining whether a flash memory die is defective;

identifying at least one defective flash memory die in a set of flash memory dies that provide a nominal initial capacity based on the at least one identified criterion; and

disabling the at least one defective flash memory die to provide a flash memory system having an operational capacity that is less than the nominal initial capacity.

2. The article of claim 1, the operations further comprising assembling the flash memory system into a flash memory package.

3. The article of claim 1, wherein the operational capacity is substantially equal to the nominal initial capacity reduced by the capacity of each of the disabled dies.

4. The article of claim 3, the operations further comprising associating the operational capacity with the flash memory package.

5. The article of claim 4, the operations further comprising labeling the flash memory package with the associated operational capacity.

6. The article of claim 1, wherein identifying at least one defective flash memory die comprises testing a flash memory package to identify at least one defective flash memory die based on the at least one criterion.

7. The article of claim 1, wherein disabling the at least one defective flash memory die comprises an operation selected from the group consisting of:

disconnecting a bond wire to supply power to the identified die;

skipping installation of a bond wire to supply power to the identified die;

laser fusing a power connection that supplies operating power to the identified die;

blowing a fuse associated with the identified die; and

, providing an incomplete signal path for power to the identified die.

8. The article of claim 1, wherein the identified at least one criterion for determining whether a flash memory die is defective comprises a threshold bit error rate, wherein a flash memory die is determined to be defective when a bit error rate for the flash memory die exceeds the threshold bit error rate.

9. The article of claim 1, wherein the identified at least one criterion for determining whether a flash memory die is defective comprises a threshold number of defective flash memory blocks, wherein a flash memory die is determined to be defective when a number of defective flash memory blocks in the flash memory die exceeds the threshold number of defective flash memory blocks.

10. The article of claim 9, wherein a defective flash memory block is identified by a flag associated with the defective flash memory block.

11. The article of claim 1, wherein disabling the at least one defective flash memory die comprises activating at least one circuit that disables access to the at least one defective flash memory die.

12. The article of claim 1, wherein disabling the at least one defective flash memory die comprises configuring a controller to prevent the at least one defective flash memory die from receiving a chip enable signal.

13. The article of claim 1, wherein the identified and disabled one or more defective flash memory dies are contained on an unpackaged wafer of flash memory dies.

14. A system for identifying and disabling defective flash memory dies, the system comprising:

a test controller device configured to identify, based on at least one criterion for determining whether a flash memory die is defective, at least one defective flash memory die in a set of flash memory dies that provide a nominal initial capacity; and

die disabling means configured to disable the at least one defective flash memory die to provide a flash memory system having an operational capacity that is less than the nominal initial capacity.

15. The system of claim 14, the system further comprising a test bed device that provides a testing environment within which the at least one defective flash memory die is identified and disabled, wherein the testing environment provided by the test bed device identifies and disables defective flash memory dies contained in one or more of the group consisting of:

an unpackaged wafer of flash memory dies, flash memory dies that are being packaged, and flash memory dies that are packaged.

16. A method for identifying and disabling defective flash memory dies, the method comprising:

identifying at least one criterion for determining whether a flash memory die is defective;

identifying at least one defective flash memory die in a set of flash memory dies that provide a nominal initial capacity based on the at least one identified criterion; and

disabling the at least one defective flash memory die to provide a flash memory system having an operational capacity that is less than the nominal initial capacity.

17. The method of claim 16, further comprising:

determining a level of aggregation of the flash memory system at which a die disabling mechanism can disable the at least one defective flash memory die; and

wherein disabling the at least one defective flash memory die comprises disabling the at least one defective flash memory die at the determined level of aggregation.

18. The method of claim 17, wherein the determined level of aggregation includes at least one of the group consisting of:

a die level, a package level, and a board level.

19. The method of claim 16, further comprising providing the flash memory system with instructions that, when executed by the flash memory system, cause the flash memory system to perform operations comprising:

determining that a threshold amount of time has elapsed for enabling the disabled at least one defective flash memory die; and

enabling the at least one disabled defective flash memory die.

20. The method of claim 16, further comprising providing the flash memory system with instructions that, when executed by the flash memory system, cause the flash memory system to perform operations comprising:

determining that memory capacity of other non-disabled flash memory dies in the set of flash memory has degraded at least a threshold amount; and

enabling the at least one disabled defective flash memory die.