METHOD FOR PROCESSING PORTIONS OF WALLS OF AN OPENING FORMED IN A SILICON SUBSTRATE

• US 20100003573A1
• Filed: 07/16/2008
• Published: 01/07/2010
• Est. Priority Date: 07/18/2007
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Jeanne, Edgard, Nizou, Sylvain
• Granted Patent: US 8,470,190 B2
• Time in Patent Office: Days
• US Class Current: 429/34
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01M 8/1226 characterised by the supporting layer
• CPC Class Codes: H01M 8/1286 Fuel cells applied on a support, e.g. miniature fuel cells deposited on silica supports
• CPC Class Codes: Y02E 60/50 Fuel cells

Abstract

A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening.

Claims

1. A method for processing at least one wall of an opening formed in a silicon substrate, successively comprising the steps of:

(a) implanting fluorine atoms into an upper portion of the wall of the opening;

(b) performing an oxidization step; and

(c) etching at least a portion of the non-implanted portion of the opening or implanting a dopant therein.

2. The method of claim 1, wherein step (a) is preceded by the steps of:

forming an oxide layer on the opening wall;

implanting dopants into the oxide layer at the level of said upper portion of the wall and at the level of an intermediary portion of the wall located under the upper portion of the wall, the dopants being selected from the group comprising boron, phosphorus, and arsenic; and

removing the oxide which has been doped at the level of the upper and intermediary portions of the wall.

3. The method of any of claim 1, wherein step (c) comprises implanting dopants into said upper portion of the wall and into the intermediary portion of the wall located under the upper portion of the wall, the dopants being selected from the group comprising boron, phosphorus, and arsenic.

4. The method of claim 1, wherein step (c) comprises the steps of deoxidizing at least an intermediary portion of the wall located under said upper portion of the wall, then of implanting dopants into the intermediary portion of the wall, the dopants being selected from the group comprising boron, phosphorus, and arsenic.

5. The method of claim 1, wherein step (c) comprises the steps of deoxidizing at least an intermediary portion of the wall located under the upper portion of the wall, then of etching, in the opening, the silicon substrate unprotected by oxide.

6. The method of claim 1, wherein step (c) is followed by a step of total deoxidation of the opening.

7. The method of claim 1, wherein the implantations of dopants and of fluorine atoms are implantations oblique with respect to the direction of the opening (3).

8. The method of claim 1, wherein the opening does not cross the substrate (1).

9. A junction vertical field-effect transistor formed in a lightly-doped N-type silicon substrate comprising, in the upper portion of the substrate, a source electrode in contact with the substrate via a heavily-doped N-type region and, in the lower substrate portion, a drain region in contact with the substrate via a heavily-doped N-type region, the source region being surrounded with openings filled with a conductor connected to the transistor gate, the walls of these openings being coated with oxide, except for deep areas from which P-type doped areas extend, said P-type doped areas being formed in accordance with the method of claim 1.

10. A silicon fuel cell support comprising non-through vertical openings and through vertical openings, the upper ends of the non-through openings emerging on active portions of the fuel cell and the upper ends of the through openings emerging on non-active portions of the fuel cell, horizontal openings being formed in depth on the walls of the vertical openings, the horizontal openings enabling forming paths between the vertical openings.