STACKED INTEGRATED CIRCUIT ASSEMBLY

• US 20100003785A1
• Filed: 09/10/2009
• Published: 01/07/2010
• Est. Priority Date: 01/25/2007
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: SOX, Stephen E., HAUHE, Mark S., WONG, Tse E., DEARDEN, Timothy E., TONOMURA, Samuel D., QUAN, Clifton, CHAN, Polwin C.
• Granted Patent: US 7,888,176 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Claims

1. A method of producing an assembly having two stacked dice, the method comprising:

fabricating a first wafer having a plurality of first dice;

fabricating a second wafer having a plurality of second dice;

applying a first solder bump to each of an at least one second die front connection pad disposed on a front surface of each second die;

dicing the second wafer into a plurality of discrete second dice;

mounting a predetermined quantity of the discrete second dice onto the first wafer such that each second die front connection pad aligns with an at least one first die back connection pad disposed upon a back surface of each first die;

melting each first solder bump;

applying a second solder bump to each of an at least one first die front connection pad disposed upon a front surface of each first die; and

dicing the first wafer into a plurality of discrete first dice having a respective discrete second die coupled to each discrete first die.

2. The method of claim 1, wherein each first die has a first semiconductor material and each second die has a second semiconductor material, the second semiconductor material differing from the first semiconductor material.

3. The method of claim 1, wherein the assembly is operable to process microwave frequency electrical signals.

4. The method of claim 1, wherein the first solder bump and the second solder bump have different melting temperatures.

5. A method of manufacturing an integrated circuit assembly, the method comprising:

providing a substrate having a top surface with at least one substrate connection pad;

providing a first flip chip integrated circuit (FFIC) disposed above the substrate;

arranging a second flip chip integrated circuit (SFIC) above the FFIC, the FFIC disposed between the substrate and the SFIC;

making a first solder connection between the substrate connection pad and the FFIC; and

making a second solder connection between the FFIC and the SFIC,

wherein a first melting temperature of the first solder connection is different than a second melting temperature of the second solder connection.

6. The method of claim 5, further comprising arranging associated connection pads of the FFIC, the SFIC, and the substrate to be coplanar with respective surfaces of the FFIC, the SFIC, and the substrate, the respective surfaces each being arranged to face corresponding solder connections.

7. A method of manufacturing an integrated circuit assembly, the method comprising:

providing a substrate having a top surface, and at least one substrate connection pad disposed upon the top surface;

providing a first flip chip integrated circuit (FFIC) comprising a FFIC front surface and opposite thereto a FFIC back surface, the FFIC front surface proximate to the substrate top surface;

at least one FFIC front connection pad disposed upon the FFIC front surface, each FFIC front connection pad aligned to at least one substrate connection pad;

electrically coupling at least one electrically conductive through die via extending from the FFIC front surface to the FFIC back surface to one FFIC front connection pad and;

disposing at least one FFIC back connection pad upon the FFIC back surface, each FFIC back connection pad electrically coupled to one through die via;

providing a die having a first semiconductor material;

providing a second flip chip integrated circuit (SFIC) comprising a SFIC front surface and opposite thereto a SFIC back surface, the SFIC front surface proximate to the FFIC back surface;

at least one SFIC front connection pad disposed upon the SFIC front surface, each SFIC front connection pad aligned to at least one FFIC back connection pad; and

a die having a second semiconductor material, the second semiconductor material differing from the first semiconductor material;

making a first solder connection between each FFIC front connection pad and each substrate connection pad, the first solder connection establishing a first gap between the FFIC front surface and the substrate; and

making a second solder connection between each SFIC front connection pad and each FFIC back connection pad, the second solder connection establishing a second gap between the SFIC front surface and the FFIC back surface, wherein a first melting temperature of the first solder connection is lower than a second melting temperature of the second solder connection,

wherein the integrated circuit assembly is operable to process microwave frequency electrical signals.

8. The method of claim 7, further comprising arranging associated connection pads of the FFIC, the SFIC, and the substrate to be coplanar with the front and back surfaces of the FFIC, the front surface of the SFIC and the top surface of the substrate, respectively.

9. The method of claim 7, wherein the FFIC and the SFIC comprise monolithic microwave integrated circuits.

10. The method of claim 7, wherein the substrate comprises a printed circuit board.

11. The method of claim 7, further comprising plating each through die via with an electrically conductive material.

12. The method of claim 7, further comprising filling each through die via with an electrically conductive material.

13. The method of claim 7, further comprising positioning each FFIC front connection pad adjacent to the through die via to which the FFIC front connection pad is electrically coupled.

14. The method of claim 7, further comprising positioning each FFIC back connection pad adjacent to the through die via to which the FFIC back connection pad is electrically coupled.

15. The method of claim 7, further comprising positioning a first underfill material in the first gap.

16. The method of claim 7, further comprising positioning a second underfill material in a subset of the second gap.

17. The method of claim 7, further comprising positioning the FFIC approximately parallel to the SFIC.

18. The method of claim 7, further comprising positioning the FFIC approximately parallel to the substrate.

19. The method of claim 7, wherein a first thickness of the first gap is about equal to a second thickness of the second gap.