INTEGRATED CIRCUIT DEVICE WITH MULTIPLE COMMUNICATION MODES AND OPERATING METHOD THEREOF

• US 20100005207A1
• Filed: 09/25/2009
• Published: 01/07/2010
• Est. Priority Date: 05/03/2002
• Status: Active Grant

• Current Assignee: Zang-Hee Cho
• Original Assignee: Zang-Hee Cho
• Inventors: Cho, Zang-Hee
• Granted Patent: US 8,157,180 B2
• Time in Patent Office: Days
• US Class Current: 710/107
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/07733 the record carrier containing at least one further contact interface not conform ISO-7816
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10297 arrangements for handling protocols designed for non-contact record carriers such as RFIDs NFCs, e.g. ISO/IEC 14443 and 18092 cryptographic protocols H04L9/00; network security protocols H04L63/00; real-time communication protocols in data switching networks H04L65/00; network protocols for data switching network services H04L67/00
• CPC Class Codes: H04L 12/40039 Details regarding the setting of the power status of a node according to activity on the bus
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling

Abstract

An integrated circuit device having multiple communication modes is provided. The integrated circuit device includes a transceiver coupled to first and second data lines. The integrated circuit device further includes a voltage control circuit. The voltage control circuit determines whether or not an external device is connected to the integrated circuit device. In the case where the external device is connected to the integrated circuit device, the voltage control circuit controls the voltage of the first data line so as to cause the external device to not recognize the integrated circuit device for a predetermined time.

Claims

1. (canceled)

2. An integrated circuit device comprising:

first and second data terminals;

a first pull-up circuit coupled to the first data terminal;

a detector circuit for detecting whether or not a voltage of the first data terminal is lower than a predetermined reference voltage and generating a detection signal as a detection result;

a flag register for storing the detection signal as a data that represents whether or not an external device is electrically connected to the integrated circuit device; and

a control circuit for controlling the first pull-up circuit in response to the data stored in the flag register,

wherein, when the external device is electrically connected to the integrated circuit device, the control circuit controls the first pull-up circuit for a predetermined time so as to cause the external device to recognize the connection of the integrated circuit device.

3. The integrated circuit device of claim 2, further comprising a second pull-up circuit, the second pull-up circuit being coupled to the second data terminal.

4. The integrated circuit device of claim 3, wherein the control circuit electrically connects the second pull-up circuit to the second data terminal for the predetermined time.

5. The integrated circuit device of claim 3, wherein the control circuit electrically isolates the second pull-up circuit from the second data terminal after the predetermined time.

6. The integrated circuit device of claim 3, wherein the control circuit includes:

a central processing unit (CPU) for receiving the data stored in the flag register and generating a control data, the control data indicating whether or not the external device is electrically connected to the integrated circuit device; and

a control register for controlling the first and second pull-up circuits in response to the control data transmitted from the central processing unit (CPU).

7. The integrated circuit device of claim 6, wherein the control register disables the detector circuit after the predetermined time.

8. The integrated circuit device of claim 3, wherein the first and second pull-up circuits have the same resistance for the predetermined time, so that the external device does not recognize the integrated circuit device.

9. The integrated circuit device of claim 2, wherein a resistance of the first pull-up circuit is varied to 1.5 KΩ

after the predetermined time so as to cause the external device to recognize the integrated circuit device.

10. The integrated circuit device of claim 2, wherein the external device does not recognize the connection state of the integrated circuit device for the predetermined time.

11. The integrated circuit device of claim 2, wherein the integrated circuit device includes a smart card supporting an ISO communication mode and a non-ISO communication mode, and the external device includes a smart card reader.

12. The integrated circuit device of claim 11, wherein, when the external device is not electrically connected to the integrated circuit device, the integrated circuit device operates in the ISO communication mode.