PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNECTED MEMORY SYSTEM
First Claim
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1. A memory hub device comprising:
- a first bus interface for communicating with a high-speed bus; and
frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data, the translating including identifying write data headers and associated write data for self-registering write to data buffer commands.
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Abstract
Systems and methods for providing a variable frame format protocol in a cascade interconnected memory system. The systems include a memory hub device that utilizes a first bus interface to communicate on a high-speed bus. The hub device also includes frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data. The translating includes identifying write data headers and associated write data for self-registering write to data buffer commands.
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Citations
20 Claims
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1. A memory hub device comprising:
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a first bus interface for communicating with a high-speed bus; and frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data, the translating including identifying write data headers and associated write data for self-registering write to data buffer commands. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for providing a variable frame format protocol in a cascade interconnected memory system, the method comprising:
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receiving frames of varying formats on a high-speed bus, the receiving at a hub device in a cascade interconnected memory system, each frame including a frame type indicator and one or more write data bits; determining placement of the write data bits in the frames, the determining responsive to the frame type indicator; monitoring contents of the write data bits; identifying a write data header for a self-registering write to data buffer command in the write data bits, the write data header specifying a length of associated write data and a target hub device identifier; identifying the associated write data in the write data bits, the identifying responsive to the write data header; and writing the associated write data to a write data buffer at the hub device in response to the hub device being identified as the target hub device. - View Dependent Claims (15, 16)
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17. A memory controller comprising:
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a first bus interface for communicating with one or more hub devices in a cascade interconnect memory system via a high-speed bus; and frame encoding logic for generating variable format frames for transmission to the hub devices, the generated frames comprising; frame type indicators for specifying locations of write data bits in the frames; and write data headers and associated write data for self-registering write to data buffer commands, the write data header and associated write located in the write data bits. - View Dependent Claims (18, 19)
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20. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
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a first bus interface for communicating with a high-speed bus; and frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data, the translating including identifying write data headers and associated write data for self-registering write to data buffer commands.
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Specification