ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM
First Claim
1. A system comprising:
- a memory controller;
a memory channel comprised of;
unidirectional downstream link segments including at least 13 data bit lanes, 2 spare bit lanes and a downstream clock, coupled to the memory controller and operable for transferring data frames configurable between 8, 12 and 16 transfers per frame, with each transfer comprised of multiple bit lanes; and
unidirectional upstream link segments including at least 20 bit lanes, 2 spare bit lanes and an upstream clock, coupled to the memory controller and operable for transferring data frames comprised of 8 transfers per frame, with each transfer comprised of multiple bit lanes;
a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device; and
multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices.
1 Assignment
0 Petitions
Accused Products
Abstract
A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
200 Citations
24 Claims
-
1. A system comprising:
-
a memory controller; a memory channel comprised of; unidirectional downstream link segments including at least 13 data bit lanes, 2 spare bit lanes and a downstream clock, coupled to the memory controller and operable for transferring data frames configurable between 8, 12 and 16 transfers per frame, with each transfer comprised of multiple bit lanes; and unidirectional upstream link segments including at least 20 bit lanes, 2 spare bit lanes and an upstream clock, coupled to the memory controller and operable for transferring data frames comprised of 8 transfers per frame, with each transfer comprised of multiple bit lanes; a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device; and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A memory hub device comprising:
-
a link interface to communicate to one or more of a memory controller and another memory hub device via a memory channel, wherein the memory channel comprises; unidirectional downstream link segments including at least 13 data bit lanes, 2 spare bit lanes and a downstream clock, coupled to the memory controller and operable for transferring data frames configurable between 8, 12 and 16 transfers per frame, with each transfer comprised of multiple bit lanes; and unidirectional upstream link segments including at least 20 bit lanes, 2 spare bit lanes and an upstream clock, coupled to the memory controller and operable for transferring data frames comprised of 8 transfers per frame, with each transfer comprised of multiple bit lanes; and a plurality of ports, wherein each port is configured to communicate to one of a memory device and a register device, wherein the register device includes address, command and control re-drive circuitry and clock re-alignment and re-drive circuitry to control access to one or more memory devices. - View Dependent Claims (11, 12, 13, 14, 15)
-
-
16. A method for providing an enhanced cascade interconnected memory system, the method comprising:
-
configuring a memory hub device to communicate with a memory controller and multiple memory devices, wherein communication between the memory hub and the memory controller is established via a memory channel, the memory channel comprising; unidirectional downstream link segments including at least 13 data bit lanes, 2 spare bit lanes and a downstream clock, coupled to the memory controller and operable for transferring data frames configurable between 8, 12 and 16 transfers per frame, with each transfer comprised of multiple bit lanes; and unidirectional upstream link segments including at least 20 bit lanes, 2 spare bit lanes and an upstream clock, coupled to the memory controller and operable for transferring data frames comprised of 8 transfers per frame, with each transfer comprised of multiple bit lanes; and configuring primary and secondary upstream and downstream transmitters and receivers of the memory hub device to communicate with the memory controller via the memory channel and one or more cascade interconnected memory hub devices. - View Dependent Claims (17, 18, 19, 20)
-
-
21. A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
-
a link interface to communicate to one or more of a memory controller and another memory hub device via a memory channel, wherein the memory channel comprises; unidirectional downstream link segments including at least 13 data bit lanes, 2 spare bit lanes and a downstream clock, coupled to the memory controller and operable for transferring data frames configurable between 8, 12 and 16 transfers per frame, with each transfer comprised of multiple bit lanes; and unidirectional upstream link segments including at least 20 bit lanes, 2 spare bit lanes and an upstream clock, coupled to the memory controller and operable for transferring data frames comprised of 8 transfers per frame, with each transfer comprised of multiple bit lanes; and a plurality of ports, wherein each port is configured to communicate to one of a memory device and a register device, wherein the register device includes address, command and control re-drive circuitry and clock re-alignment and re-drive circuitry to control access to one or more memory devices. - View Dependent Claims (22, 23, 24)
-
Specification