CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY

• US 20100005366A1
• Filed: 07/01/2008
• Published: 01/07/2010
• Est. Priority Date: 07/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E., Trombley, Michael R., Dell, Timothy J.
• Granted Patent: US 8,245,105 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device. Responding to the error includes recording a severity level of the failure in the FIR and taking an action at the hub device that is responsive to the severity level of the failure. The action includes one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.

Claims

1. A hub device comprising:

an interface to a high speed bus for communicating with a memory controller, the memory controller and the hub device included in a cascade interconnect memory system and the high-speed bus including bit lanes and one or more clock lanes;

a bi-directional fault signal line in communication with the memory controller and readable by a service interface;

a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and

error recovery logic for responding to a failure detected at the hub device, the responding including;

recording a severity level of the failure in the FIR; and

taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.

2. The hub device of claim 1 wherein the severity level is fault and the hub device notifies the memory controller of the failure via the fault signal line, preserves contents of internal latches and memory devices in response to the hub device operating in a slow clock mode, asserts fences and turns off logical clocks.

3. The hub device of claim 2 wherein the failure is one or both of an uncorrectable error and a hard error.

4. The hub device of claim 1 wherein the severity level is recoverable and the hub device notifies the memory controller of the failure by transmitting a poisoned CRC to the memory controller via the high speed bus and preserves contents of internal latches and memory devices.

5. The hub device of claim 4 wherein the hub device is in communication with a downstream hub device via the high speed bus and the hub device further initiates a clock repair and detection training state on the downstream hub device in response to the failure occurring in a clock received from the downstream hub device.

6. The hub device of claim 4 wherein the failure is one or both of a correctable error and a persistent soft error.

7. The hub device of claim 1 wherein the severity level is attention and the hub device records the failure and notifies the memory controller of the failure.

8. The hub device of claim 7 wherein the failure is one or more of a zero error and a temporary soft error.

9. The hub device of claim 1 wherein the severity level is information and the hub device records the failure at the hub device and notifies the memory controller of the failure.

10. The hub device of claim 1 wherein the failure is one or more of a clock error, an internal hub device logic error, a channel error, and a thermal error.

11. A high reliability cascade interconnect memory system comprising:

a memory controller;

a unidirectional downstream channel including multiple bit lanes and clock lanes, the downstream channel in communication with the memory controller and operable for transferring data frames comprised of eight, twelve or sixteen transfers;

a unidirectional upstream channel including multiple bit lanes and clock lanes, the downstream channel in communication with the memory controller and operable for transferring data frames comprised of eight transfers;

a hub device in communication with a plurality of memory devices and in communication with both the downstream and upstream channels for communicating with the memory controller via direct connection or via a cascade interconnection through an other hub device, the hub device comprising;

a bi-directional fault signal line in communication with the memory controller and readable by a service interface;

a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and

error recovery logic for responding to a failure detected at the hub device, the responding including;

recording a severity level of the failure in the FIR; and

taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.

12. The memory system of claim 11 wherein the hub device notifies the memory controller of the failure and the memory controller responds to the notification by de-allocating all or portions of the memory system, by entering a lane shadowing procedure, by performing re-initialization and repair of all or portions of the memory system or by initiating a retry of a command sequence.

13. The memory system of claim 11 wherein the severity level is fault and the hub device notifies the memory controller of the failure via the fault signal line, preserves contents of internal latches and memory devices in response to the hub device operating in a slow clock mode, asserts fences and turns off logical clocks.

14. The memory system of claim 11 wherein the severity level is recoverable and the hub device notifies the memory controller of the failure by transmitting a poisoned CRC to the memory controller via the high speed bus and preserves contents of internal latches and memory devices.

15. The memory system of claim 14 wherein the hub device further initiates a clock repair and detection training state on the downstream hub device in response to the failure occurring in a clock received from the downstream hub device.

16. The memory system of claim 11 wherein the severity level is attention or information and the hub device records the failure and notifies the memory controller of the failure.

17. A method for processing errors in a memory system, the method comprising:

detecting a failure having a severity level at a hub device in a cascade interconnect memory system, the memory system including the hub device and a memory controller;

recording the severity level in a FIR at the hub device;

notifying the memory controller of the failure via a fault signal line, preserving contents of internal latches and memory devices in response to the hub device operating in a slow clock mode, and asserting fences and turning off logical clocks at the hub device in response to the severity level being equal to fault;

notifying the memory controller of the failure by transmitting a poisoned cyclical redundancy code (CRC) to the memory controller, and preserving contents of internal latches and memory devices in response to the severity level being equal to recoverable; and

recording the failure at the memory device in response to the severity level being equal to attention.

18. The method of claim 17 wherein the hub device is in communication with a downstream hub device and a clock repair and detection training state is initiated on the downstream hub device in response to the failure occurring in a clock received from the downstream hub device and to the severity level being equal to recoverable.

19. The method of claim 17 wherein the failure is one or more of a clock error, a channel error, an internal hub device logic error, and a thermal error.

20. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a hub device comprising;

an interface to a high speed bus for communicating with a memory controller, the memory controller and the hub device included in a cascade interconnect memory system and the high-speed bus including bit lanes and one or more clock lanes;

a bi-directional fault signal line in communication with the memory controller and readable by a service interface;

a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and

error recovery logic for responding to a failure detected at the hub device, the responding including;

recording a severity level of the failure in the FIR; and

taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.