CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY
First Claim
1. A hub device comprising:
- an interface to a high speed bus for communicating with a memory controller, the memory controller and the hub device included in a cascade interconnect memory system and the high-speed bus including bit lanes and one or more clock lanes;
a bi-directional fault signal line in communication with the memory controller and readable by a service interface;
a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and
error recovery logic for responding to a failure detected at the hub device, the responding including;
recording a severity level of the failure in the FIR; and
taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.
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Accused Products
Abstract
A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device. Responding to the error includes recording a severity level of the failure in the FIR and taking an action at the hub device that is responsive to the severity level of the failure. The action includes one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.
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Citations
20 Claims
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1. A hub device comprising:
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an interface to a high speed bus for communicating with a memory controller, the memory controller and the hub device included in a cascade interconnect memory system and the high-speed bus including bit lanes and one or more clock lanes; a bi-directional fault signal line in communication with the memory controller and readable by a service interface; a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and error recovery logic for responding to a failure detected at the hub device, the responding including; recording a severity level of the failure in the FIR; and taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A high reliability cascade interconnect memory system comprising:
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a memory controller; a unidirectional downstream channel including multiple bit lanes and clock lanes, the downstream channel in communication with the memory controller and operable for transferring data frames comprised of eight, twelve or sixteen transfers; a unidirectional upstream channel including multiple bit lanes and clock lanes, the downstream channel in communication with the memory controller and operable for transferring data frames comprised of eight transfers; a hub device in communication with a plurality of memory devices and in communication with both the downstream and upstream channels for communicating with the memory controller via direct connection or via a cascade interconnection through an other hub device, the hub device comprising; a bi-directional fault signal line in communication with the memory controller and readable by a service interface; a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and error recovery logic for responding to a failure detected at the hub device, the responding including; recording a severity level of the failure in the FIR; and taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method for processing errors in a memory system, the method comprising:
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detecting a failure having a severity level at a hub device in a cascade interconnect memory system, the memory system including the hub device and a memory controller; recording the severity level in a FIR at the hub device; notifying the memory controller of the failure via a fault signal line, preserving contents of internal latches and memory devices in response to the hub device operating in a slow clock mode, and asserting fences and turning off logical clocks at the hub device in response to the severity level being equal to fault; notifying the memory controller of the failure by transmitting a poisoned cyclical redundancy code (CRC) to the memory controller, and preserving contents of internal latches and memory devices in response to the severity level being equal to recoverable; and recording the failure at the memory device in response to the severity level being equal to attention. - View Dependent Claims (18, 19)
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20. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a hub device comprising; an interface to a high speed bus for communicating with a memory controller, the memory controller and the hub device included in a cascade interconnect memory system and the high-speed bus including bit lanes and one or more clock lanes; a bi-directional fault signal line in communication with the memory controller and readable by a service interface; a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and error recovery logic for responding to a failure detected at the hub device, the responding including; recording a severity level of the failure in the FIR; and taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.
Specification