METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING

• US 20100005470A1
• Filed: 07/02/2008
• Published: 01/07/2010
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Cradle IP LLC
• Original Assignee: Cradle Technologies
• Inventors: Machnicki, Erik P., Simon, Moshe B., Harrison, David A.
• Granted Patent: US 8,151,008 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/30 with priority control

Abstract

A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.

Claims

1. A direct memory access (DMA) engine processing transfer requests of a data processing system, comprising:

a command processor adapted to receive and interpret transfer requests of the data processing system;

a transaction dispatcher having read, read response, write engines adapted to handle command and data octet transfers through a set of FIFO registers to and from a DRAM controller and a global bus interface in accord with transfer requests interpreted by the command processor; and

a channel scanner having a deadline engine and a transaction controller, the deadline engine adapted to determine a transfer urgency, and the transaction controller adapted to schedule among multiple transfer requests interpreted by the command processor based on the determined transfer urgency of the respective transfer requests so as to control the engines of the transaction dispatcher, wherein the transfer urgency is based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes.

2. The DMA engine as in claim 1, wherein the transaction controller is further adapted to preempt processing of a current transfer by the transaction dispatcher whenever a higher urgency request is received.

3. The DMA engine as in claim 1, wherein the transaction controller assigns one of four priorities ranging from high (0) to low (3), with priority 0 representing hard real-time transfers where there is no penalty if the transfer completes by the deadline and the penalty for missing a deadline is severe, priority 1 representing high-priority zero-deadline soft real-time transfers where there is a definite penalty in a critical path no matter how early the transfer is completed and the penalty increases with completion time, priority 2 representing low-priority zero-deadline soft real-time transfers where there is a definite penalty in a non-critical path no matter how early the transfer is completed and the penalty increases with completion time, and priority 3 representing soft real-time transfers where there is no penalty if the transfer completes by the deadline and the penalty for missing a deadline is tolerable.

4. The DMA engine as in claim 3, wherein the transaction controller is further adapted to schedule transfer requests in timeslices according to priority so as to bound latency of lower priority transfer requests, and with priority 0 transfer requests having the largest timeslice.

5. The DMA engine as in claim 4, wherein priority 0 transfer requests are assigned to a first timeslice and priority 1, 2 and 3 transfer requests are all assigned to a second timeslice.

6. The DMA engine as in claim 3, wherein the set of FIFO registers include a set of command FIFO registers, each servicing a different transfer priority.

7. The DMA engine as in claim 1, wherein the transaction controller is adapted to post service requests of the transaction dispatcher for preparing a next data transfer transaction while a current data transfer transaction by the transaction dispatcher is still in progress.

8. A method of processing direct memory access (DMA) transfer requests of a data processing system, comprising:

interpreting transfer requests received from the data processing system;

determining a transfer urgency for the transfer requests based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes;

scheduling among multiple transfer requests based on the determined transfer urgency; and

controlling command and data octet transfers through a set of FIFO registers to and from a DRAM controller and a global bus interface in accord with the scheduled transfer requests.

9. The method as in claim 8, further comprising preempting a current transfer whenever a higher urgency request is received.

10. The method as in claim 8, wherein the determining of a transfer urgency includes assigning one of four priorities ranging from high (0) to low (3) to each received transfer request, with priority 0 representing hard real-time transfers where there is no penalty if the transfer completes by the deadline and the penalty for missing a deadline is severe, priority 1 representing high-priority zero-deadline soft real-time transfers where there is a definite penalty in a critical path no matter how early the transfer is completed and the penalty increases with completion time, priority 2 representing low-priority zero-deadline soft real-time transfers where there is a definite penalty in a non-critical path no matter how early the transfer is completed and the penalty increases with completion time, and priority 3 representing soft real-time transfers where there is no penalty if the transfer completes by the deadline and the penalty for missing a deadline is tolerable.

11. The method as in claim 10, wherein transfer requests are scheduled in timeslices according to priority so as to bound latency of lower priority transfer requests, with priority 0 transfer requests having the largest timeslice.

12. The method as in claim 11, wherein priority 0 transfer requests are assigned to a first timeslice and priority 1, 2 and 3 transfer requests are all assigned to a second timeslice.

13. The method as in claim 10, wherein each of a set of command FIFO registers services a different transfer priority.

14. The method as in claim 8, wherein service requests for preparing a next data transfer transaction are posted to a transaction dispatcher while a current data transfer transaction by the transaction dispatcher is still in progress.

15. The method as in claim 8, wherein a burst of multiple data transfers corresponding to a single transfer request are performed.