METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING
First Claim
1. A direct memory access (DMA) engine processing transfer requests of a data processing system, comprising:
- a command processor adapted to receive and interpret transfer requests of the data processing system;
a transaction dispatcher having read, read response, write engines adapted to handle command and data octet transfers through a set of FIFO registers to and from a DRAM controller and a global bus interface in accord with transfer requests interpreted by the command processor; and
a channel scanner having a deadline engine and a transaction controller, the deadline engine adapted to determine a transfer urgency, and the transaction controller adapted to schedule among multiple transfer requests interpreted by the command processor based on the determined transfer urgency of the respective transfer requests so as to control the engines of the transaction dispatcher, wherein the transfer urgency is based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes.
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Accused Products
Abstract
A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.
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Citations
15 Claims
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1. A direct memory access (DMA) engine processing transfer requests of a data processing system, comprising:
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a command processor adapted to receive and interpret transfer requests of the data processing system; a transaction dispatcher having read, read response, write engines adapted to handle command and data octet transfers through a set of FIFO registers to and from a DRAM controller and a global bus interface in accord with transfer requests interpreted by the command processor; and a channel scanner having a deadline engine and a transaction controller, the deadline engine adapted to determine a transfer urgency, and the transaction controller adapted to schedule among multiple transfer requests interpreted by the command processor based on the determined transfer urgency of the respective transfer requests so as to control the engines of the transaction dispatcher, wherein the transfer urgency is based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of processing direct memory access (DMA) transfer requests of a data processing system, comprising:
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interpreting transfer requests received from the data processing system; determining a transfer urgency for the transfer requests based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes; scheduling among multiple transfer requests based on the determined transfer urgency; and controlling command and data octet transfers through a set of FIFO registers to and from a DRAM controller and a global bus interface in accord with the scheduled transfer requests. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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Specification