ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON

• US 20100005649A1
• Filed: 09/17/2009
• Published: 01/14/2010
• Est. Priority Date: 07/26/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Kim, Deok-kee, Li, Wai-Kin
• Granted Patent: US 7,785,937 B2
• Time in Patent Office: Days
• US Class Current: 29/623
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: Y10T 29/49107 Fuse making

Abstract

An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

Claims

1. A method of forming a semiconductor structure comprising:

forming an electrical fuse comprising a first electrode, a second electrode, and a fuselink on shallow trench isolation in a semiconductor substrate;

forming a first dielectric layer on said electrical fuse;

forming a polymeric matrix comprising a first polymeric block component and containing cylindrical holes having a sublithographic diameter on said first dielectric layer;

forming a plurality of cylindrical holes having said sublithographic diameter in said first dielectric layer by etching said first dielectric layer; and

depositing a second dielectric layer and forming a plurality of cylindrical cavities within said cylindrical holes, wherein said second dielectric layer extends into each of said cylindrical holes and encapsulates said cylindrical cavities.

2. The method of claim 1, further comprising:

applying a block copolymer on said first dielectric layer, wherein said block copolymer comprises at least said first polymeric block component and a second polymeric block component that are immiscible with each other;

annealing said block copolymer to form a plurality of cylindrical blocks comprising said second polymeric block component and having said sublithographic diameter and embedded in said polymeric matrix; and

selectively removing said second polymeric block component relative to said polymeric matrix.

3. The method of claim 2, further comprising:

forming a dielectric template layer on said first dielectric layer; and

forming an opening having lithographic dimensions in said dielectric template layer over said fuselink.

4. The method of claim 1, wherein said depositing of said second dielectric layer is a non-conformal process that deposits less material on a lower portion than on a top portion within each of said plurality of cylindrical holes and forms a conical cavity top.

5. The method of claim 1, wherein said plurality of cylindrical cavities is separated from said fuselink by a sublithographic dimension.

6. The method of claim 1, further comprising forming a dielectric spacer directly on sidewalls of said electrical fuse, wherein said plurality of cylindrical cavities is formed above said dielectric spacer and said shallow trench isolation and is separated from said dielectric spacer and said shallow trench isolation by portions of said second dielectric layer having a sublithographic thickness.

7. The method of claim 1, wherein said first dielectric layer comprises a first dielectric material selected from the group consisting of a silicon oxide, a silicon nitride, a chemical vapor deposition (CVD) low-k dielectric material, and a spin-on low-k dielectric material, and said second dielectric layer comprises a second dielectric material selected from the group consisting of a silicon oxide, a silicon nitride, and a chemical vapor deposition (CVD) low-k dielectric material.