STRUCTURE AND PROCESS OF EMBEDDED CHIP PACKAGE

• US 20100006330A1
• Filed: 06/26/2009
• Published: 01/14/2010
• Est. Priority Date: 11/07/2008
• Status: Abandoned Application

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Ou, Ying-Te, Wang, Yung-Hui, Fu, Chieh-Chen
• Application Number:
  US12/493,065
• Publication Number:
  US 20100006330A1
• Time in Patent Office: Days
• US Class Current: 174/260
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H05K 1/056 : the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/445 : having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4608 : comprising an electrically conductive base or core
• CPC Class Codes: Y10T 29/49172 : by molding of insulating material

Abstract

A process of an embedded chip package structure includes following steps. Firstly, a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a number of through holes are provided. The opening and the through holes connect the first surface and the second surface. A chip is then disposed in the opening. Next, a dielectric layer is formed in the opening and the through holes to fix the chip in the opening. Thereafter, a number of conductive vias are respectively formed in the through holes and insulated from the metal core layer by a portion of the dielectric layer located in the through holes. A circuit structure is then formed on the first surface of the metal core layer by performing a build-up process, and the circuit structure electrically connects the chip and the conductive vias.

Claims

1. A process of an embedded chip package, comprising:

providing a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a plurality of first through holes, wherein the opening and the plurality of first through holes penetrate the metal core layer;

disposing a chip in the opening;

forming a dielectric layer in the opening and the plurality of first through holes and fixing the chip in the opening;

respectively forming a plurality of conductive vias in the plurality of first through holes, the plurality of conductive vias being insulated from the metal core layer by a portion of the dielectric layer located in the plurality of first through holes; and

forming a first circuit structure on the first surface of the metal core layer by performing a build-up process, the first circuit structure electrically connecting the chip and the plurality of conductive vias.

2. The process of the embedded chip package as claimed in claim 1, further comprising:

forming a second circuit structure on the second surface of the metal core layer by performing a build-up process after forming the plurality of conductive vias, the second circuit structure electrically connecting the plurality of conductive vias.

3. The process of the embedded chip package as claimed in claim 2, further comprising:

forming a plurality of solder balls on the first circuit structure or the second circuit structure after forming the second circuit structure, the plurality of solder balls electrically connecting the first circuit structure or the second circuit structure.

4. The process of the embedded chip package as claimed in claim 1, further comprising:

forming a surface finish after forming the first circuit structure, the surface finish covering a pad of the first circuit structure.

5. The process of the embedded chip package as claimed in claim 1, further comprising:

polishing a portion of the dielectric layer located outside the opening and the plurality of first through holes after forming the dielectric layer, such that the dielectric layer is merely positioned in the opening and the plurality of first through holes.

6. The process of the embedded chip package as claimed in claim 1, further comprising:

respectively forming a plurality of second through holes on the portion of the dielectric layer located in the plurality of first through holes before forming the plurality of conductive vias, diameters of the plurality of second through holes being smaller than diameters of the plurality of first through holes;

forming a seed layer on inner walls of the plurality of second through holes; and

a portion of the seed layer located in the plurality of second through holes to form the plurality of conductive vias.

7. The process of the embedded chip package as claimed in claim 6, further comprising:

forming a patterned plating-resistant layer before forming the plurality of conductive vias, the patterned plating-resistant layer covering the portion of the seed layer located on the first surface and the second surface, a plurality of openings of the patterned plating-resistant layer respectively exposing the plurality of second through openings;

electroplating the plurality of conductive vias in the plurality of second through holes when forming the plurality of conductive vias; and

removing the patterned plating-resistant layer and a portion of the seed layer not covered by the plurality of the conductive vias after forming the plurality of the conductive vias.

8. The process of the embedded chip package as claimed in claim 1, further comprising:

adhering a thermal release material to the first surface of the metal core layer before disposing the chip in the opening, wherein the thermal release material covers the plurality of first through holes and the opening;

affixing the chip to the thermal release material when disposing the chip in the opening; and

removing the thermal release material after forming the dielectric layer.

9. The process of the embedded chip package as claimed in claim 8, wherein the chip has an active surface and a back surface opposite to the active surface, and the active surface faces the thermal release material.

10. The process of the embedded chip package as claimed in claim 9, wherein the active surface of the chip, a first surface of the dielectric layer, and the first surface of the metal core layer are substantially flush.

11. The process of the embedded chip package as claimed in claim 9, wherein the back surface of the chip, a second surface of the dielectric layer, and the second surface of the metal core layer are substantially flush.

12. An embedded chip package structure, comprising:

a metal core layer, having a first surface, a second surface opposite to the first surface, an opening, and a plurality of first through holes, wherein the opening and the plurality of first through holes penetrate the metal core layer,

a dielectric layer, disposed in the plurality of first through holes and the opening;

a chip, embedded in a portion of the dielectric layer located in the opening;

a plurality of conductive vias, respectively disposed in the plurality of first through holes and insulated from the metal core layer by a portion of the dielectric layer located in the plurality of first through holes; and

a first circuit structure, disposed on the first surface of the metal core layer and electrically connected to the chip and the plurality of conductive vias.

13. The embedded chip package structure as claimed in claim 12, further comprising:

a second circuit structure, disposed on the second surface of the metal core layer and electrically connected to the plurality of conductive vias.

14. The embedded chip package structure as claimed in claim 13, further comprising:

a plurality of solder balls, disposed on and electrically connected to the first circuit structure or the second circuit structure.

15. The embedded chip package structure as claimed in claim 12, further comprising:

a surface finish, covering a pad of the first circuit structure.

16. The embedded chip package structure as claimed in claim 12, wherein the dielectric layer exposes an active surface of the chip.

17. The embedded chip package structure as claimed in claim 16, wherein the active surface of the chip, a first surface of the dielectric layer, and the first surface of the metal core layer are substantially flush.

18. The embedded chip package structure as claimed in claim 12, wherein the dielectric layer exposes a back surface of the chip, and the back surface is opposite to an active surface of the chip.

19. The embedded chip package structure as claimed in claim 18, wherein the back surface of the chip, a second surface of the dielectric layer, and the second surface of the metal core layer are substantially flush.

20. The embedded chip package structure as claimed in claim 12, further comprising:

a seed layer, disposed between the plurality of conductive vias and the dielectric layer.