SYSTEM COMPRISED OF A CHIP AND A SUBSTRATE AND METHOD OF ASSEMBLING SUCH A SYSTEM

• US 20100006653A1
• Filed: 09/25/2007
• Published: 01/14/2010
• Est. Priority Date: 10/09/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Salfelner, Anton
• Granted Patent: US 8,136,737 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07745 Mounting details of integrated circuit chips
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81121 Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49137 : Different components

Abstract

A system comprises a chip (71) and a substrate (78). The chip (71) comprises a circuitry and a mounting surface (83) with first and second contacts (73, 74, 75, 76). The substrate (78) comprises a surface (90) with first and second contact pads (79, 80) and an electrically conductive pad (91) connected to the first contact pad (79) by a low-resistive connection (93). The chip (71) is attached to the substrate (78) so that the mounting surface (83) is spaced apart from the first contact pad (75) and the electrically conductive pad (91). The mounting surface (83) overlaps partly the first contact pad (79) with a first overlapping area (B1) resulting in a first stray capacitor (C₁) and the electrically conductive pad (91) with a second overlapping area (B3) resulting in a second stray capacitor (C₃). The first contact pad (79) and the electrically conductive pad (91) are arranged on the surface (90) of the substrate (78) such that, if the chip (21) is misaligned laterally in respect to the surface (90), then the first overlapping area (B1) increases while the second overlapping area (B3) decreases, or the first overlapping area (B1) decreases while the second overlapping area (B3) increases.

Claims

1. A system, comprising:

a chip that includes circuitry and a mounting surface (83) with first and second contacts as inputs for the circuitry; and

a substrate with a surface which includes a first contact pad, a second contact pad, and an electrically conductive pad connected to the first contact pad by a low-resistive connection;

wherein the chip being attached to the substrate with the mounting surface facing toward the surface of the substrate so that the mounting surface is spaced apart from the first contact pad and the electrically conductive pad, the mounting surface partly overlapping the first contact pad with a first overlapping area and the electrically conductive pad with a second overlapping area so that the overlapped part of the first contact pad forms a first stray capacitor and the overlapped part of the electrically conductive pad forms a second stray capacitor with the mounting surface, and the first contact pad and the electrically conductive pad are arranged on the surface of the substrate such that, if the chip is misaligned laterally in respect to the surface of the substrate, then the first overlapping area increases while the second overlapping area decreases or the first overlapping area decreases while the second overlapping area increases.

2. The system according to claim 1, wherein the first contact pad and the electrically conductive pad are arranged on the surface of the substrate so that the first overlapping area decreases by the same amount as the second overlapping area increases or the first overlapping area increases by the same amount as the second overlapping area decreases, when the chip is misaligned.

3. The system according to claim 1, wherein the mounting surface is rectangular shaped and comprises four corners, and the first contact pad and the electrically conductive pad are located on the surface of the substrate so that a first corner of the four corners overlaps partly the first contact pad and a second corner of the corners being opposite to the first corner overlaps partly the electrically conductive pad.

4. The system according to claim 1, wherein the mounting surface is rectangular shaped and comprises four edges, the first contact pad and the electrically conductive pad are located on the surface of the substrate so that a first edge of the four edges overlaps partly the first contact pad and a second edge of the edges being opposite to the first edge overlaps partly the electrically conductive pad.

5. The system according to claim 1, wherein the second contact is connected to the mounting surface by a low resistive and/or a high capacitate path.

6. The system according to claim 1, further comprising:

an antenna arranged on the surface of the substrate and connected to the first and second contact pads.

7. The system according to claim 1, further comprising:

a further substrate; and

an antenna arranged on the further substrate and electrically connected to the first and second contact pads.

8. A method for producing a system comprised of a chip attached to a substrate, the method comprising the steps of:

mounting the chip, which includes circuitry and a mounting surface with first and second contacts as inputs for the circuitry, with the mounting surface on a surface of the substrate, wherein the surface includes a first contact pad, a second contact pad, and an electrically conductive pad; and

connecting the first contact with the first contact pad and the second contact with the second contact pad so that the mounting surface is spaced apart from the first contact pad and the electrically conductive pad such that the mounting surface overlaps partly the first contact pad with a first overlapping area and the electrically conductive pad with a second overlapping area so that the overlapped part of the first contact pad forms a first-stray capacitor and the overlapped part of the electrically conductive pad forms a second stray capacitor with the mounting surface;

orientating the first contact pad and the electrically conductive pad on the surface of the substrate such that if the chip is misaligned laterally in respect to the surface of the substrate, then the first overlapping area increases when the second overlapping area decreases or the first overlapping area decreases when the second overlapping area increases.

9. The method according to claim 8, further comprising:

orientating the first contact pad and the electrically conductive pad on the surface of the substrate so that the first overlapping area decreases by the same amount as the second overlapping area increases or the first overlapping area increases by the same amount as the second overlapping area decreases, when the chip is misaligned.

10. The method according to claim 8, wherein the mounting surface is rectangular shaped and comprises four corners, the method further comprising:

orientating the first contact pad and the electrically conductive pad on the surface of the substrate so that a first corner of the four corners overlaps partly the first contact pad and a second corner of the four corners being opposite to the first corner overlaps partly the electrically conductive pad.

11. The method according to claim 8, wherein the mounting surface is rectangular shaped and comprises four edges, the method further comprising:

orientating the first contact pad and the electrically conductive pad on the surface of the substrate so that a first edge of the four edges overlaps partly the first contact pad and a second edge of the four edges being opposite to the first edge overlaps partly the electrically conductive pad.

12. The method according to claim 8, further comprising:

connecting the second contact to the mounting surface by a low resistive or a high capacitive path.

13. The method according to claim 8, further comprising:

connecting the second contact to the mounting surface by a low resistive and high capacitive path.