THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME

• US 20100006833A1
• Filed: 02/26/2009
• Published: 01/14/2010
• Est. Priority Date: 07/08/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Chung, Hyun-Joong, Kim, Min-Kyu, Choi, Chaun-Gi, Lee, Jong-Hyuk, Yang, Hui-Won, Ha, Jae-Heung, Mo, Yeon-Gon, Song, Young-Woo, Jeong, Jae-Kyeong, Kim, Kwang-Suk, Jeong, Jong-Han
• Granted Patent: US 8,178,884 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor, a method of manufacturing the thin film transistor, and a flat panel display device including the thin film transistor. The thin film transistor includes: a gate electrode formed on a substrate; a gate insulating film formed on the gate electrode; an activation layer formed on the gate insulating film; a passivation layer including a compound semiconductor oxide, formed on the activation layer; and source and drain electrodes that contact the activation layer.

Claims

1. A thin film transistor, comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating film formed on the gate electrode and the substrate;

an activation layer formed on the gate insulating layer and insulated from the gate electrode by the gate insulating film, the activation layer comprising, a compound semiconductor oxide or zinc oxide (ZnO);

a passivation layer formed on the activation layer, comprising an inorganic oxide; and

source and drain electrodes that contact the activation layer.

2. The thin film transistor as claimed in claim 1, wherein the source and drain electrodes contact the activation layer, through contact holes formed in the passivation layer.

3. The thin film transistor as claimed in claim 1, wherein the compound semiconductor oxide consists of zinc oxide (ZnO).

4. The thin film transistor as claimed in claim 3, wherein the compound semiconductor oxide is doped with at least one ion of gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), and vanadium (V).

5. The thin film transistor as claimed in claim 1, wherein the inorganic oxide comprises elements that are also comprised in the compound semiconductor oxide.

6. The thin film transistor as claimed in claim 5, wherein the compound semiconductor oxide comprises gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), vanadium (V), or a combination thereof.

7. The thin film transistor as claimed in claim 1, wherein the inorganic oxide comprises silicon (Si) or aluminum (Al).

8. The thin film transistor as claimed in claim 1, wherein the inorganic oxide comprises silicon oxide (SiO₂), aluminum oxide (Al₂O₃), gallium oxide (GaO), hafnium oxide (HfO), or aluminum oxynitride (ALON).

9. The thin film transistor as claimed in claim 1, further comprising a buffer layer formed between the substrate and the gate electrode.

10. A method of manufacturing a thin film transistor, comprising:

forming a gate electrode on a substrate;

forming a gate insulating film on the gate electrode;

forming an activation layer comprising a compound semiconductor oxide or zinc oxide (ZnO), on the gate insulating film;

forming a passivation layer comprising an inorganic oxide, on the activation layer; and

forming source and drain electrodes in contact with the activation layer.

11. The method of manufacturing the thin film transistor as claimed in claim 10, wherein the forming of the passivation layer comprises:

forming contact holes in the passivation layer.

12. The method of manufacturing the thin film transistor as claimed in claim 11, wherein the forming of the source and drain electrodes comprises:

forming a conductive layer on the passivation layer and in the contact holes; and

patterning the conductive layer to form the source and drain electrodes, which contact the activation layer through the contact holes.

13. The method of manufacturing the thin film transistor as claimed in claim 10, further comprising annealing the passivation layer.

14. The method of manufacturing the thin film transistor as claimed in claim 10, wherein the activation layer comprises zinc oxide (ZnO).

15. The method of manufacturing the thin film transistor as claimed in claim 14, wherein the compound semiconductor oxide is doped with at least one ion of gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), and vanadium (V).

16. The method of manufacturing the thin film transistor as claimed in claim 10, wherein the inorganic oxide comprises elements that are also comprised in the compound semiconductor oxide.

17. The method of manufacturing the thin film transistor as claimed in claim 16, wherein the compound semiconductor oxide comprises gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), vanadium (V), or a combination thereof.

18. The method of manufacturing the thin film transistor as claimed in claim 10, wherein the inorganic oxide comprises silicon (Si) or aluminum (Al).

19. The method of manufacturing the thin film transistor as claimed in claim 10, wherein the forming of the source and drain electrodes comprises using the passivation layer as an etch stop layer.

20. The method of manufacturing the thin film transistor as claimed in claim 10, further comprising forming a buffer layer on the substrate.

21. A flat panel display device, comprising:

opposing first and second substrates;

pixel electrodes disposed on the first substrate

scan and data lines disposed on the first substrate, around the pixel electrodes;

thin film transistors connected to the scan lines, the data lines, and the pixel electrodes, to control the operations of the pixel electrodes, the thin film transistors each comprising,

a gate electrode formed on the first substrate,

a gate insulating film formed on the gate electrode and the first substrate,

an activation layer formed on the gate insulating layer and insulated from the gate electrode by the insulating layer, the activation layer comprising a compound semiconductor oxide or zinc oxide (ZnO),

a passivation layer formed on the activation layer, comprising an inorganic oxide, and

source and drain electrodes that contact the activation layer;

a common electrode disposed on the second substrate; and

a liquid crystal layer injected into a space between the first and second substrates.

22. The flat panel display device as claimed in claim 21, wherein the source and drain electrodes contact the activation layer, through contact holes formed in the passivation layer.

23. The flat panel display device as claimed in claim 21, wherein the activation layer comprises zinc oxide (ZnO).

24. The flat panel display device as claimed in claim 23, wherein the activation layer is doped with at least one ion of gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), and vanadium (V).

25. The flat panel display device as claimed in claim 21, wherein the inorganic oxide comprises elements that are also comprised in the compound semiconductor oxide.

26. The flat panel display device as claimed in claim 25, wherein the compound semiconductor oxide comprises gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), vanadium (V), or a combination thereof.

27. The flat panel display device as claimed in claim 21, wherein the inorganic oxide comprises silicon (Si) or aluminum (Al).

28. A flat panel display device, comprising:

opposing first and second substrates;

organic light emitting devices disposed on the first substrate;

scan and data lines disposed on the first substrate, around the organic light emitting devices;

thin film transistors disposed connected to the scan lines, the data lines, and the organic light emitting devices, to control the operation of the organic light emitting devices, the thin film transistors each comprising,

a gate electrode formed on the first substrate,

a gate insulating film formed on the gate electrode and the first substrate,

an activation layer formed on the gate insulating layer and insulated from the gate electrode by the gate insulating film, the activation layer comprising a compound semiconductor oxide or zinc oxide (ZnO),

a passivation layer formed on the activation layer, comprising an inorganic oxide, and

source and drain electrodes that contact the activation layer.

29. The flat panel display device as claimed in claim 28, wherein the source and drain electrodes extend through holes in the passivation layer to contact the activation layer.

30. The flat panel display device as claimed in claim 28, wherein the activation layer comprises zinc oxide (ZnO).

31. The flat panel display device as claimed in claim 30, wherein the activation layer is doped with at least one ion of gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), and vanadium (V).

32. The flat panel display device as claimed in claim 28, wherein the inorganic oxide is formed of elements that are also comprised in the compound semiconductor oxide.

33. The flat panel display device as claimed in claim 32, wherein the compound semiconductor oxide comprises gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), vanadium (V), or a combination thereof.

34. The flat panel display device as claimed in claim 28, wherein the inorganic oxide comprises silicon (Si) or aluminum (Al).

35. A thin film transistor, comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating film formed on the gate electrode and the substrate;

an activation layer formed on the gate insulating layer, adjacent to the gate electrode, the activation layer comprising ZnO, ZnGaO, ZnInO, ZnSnO, or GaInZnO;

a passivation layer formed on the activation layer, comprising an inorganic oxide; and

source and drain electrodes that contact the activation layer.

36. The thin film transistor of claim 35, wherein the band gap of the passivation layer no larger than the band gap of the activation layer.