BACKSIDE ILLUMINATED IMAGE SENSOR WITH SHALLOW BACKSIDE TRENCH FOR PHOTODIODE ISOLATION

• US 20100006908A1
• Filed: 07/09/2008
• Published: 01/14/2010
• Est. Priority Date: 07/09/2008
• Status: Abandoned Application

• Current Assignee: Eastman Kodak Company
• Original Assignee: Eastman Kodak Company
• Inventors: Brady, Frederick T.
• Application Number:
  US12/169,810
• Publication Number:
  US 20100006908A1
• Time in Patent Office: Days
• US Class Current: 257/291
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Claims

1. A wafer level processing method for forming a plurality of image sensors each having a pixel array configured for backside illumination, the image sensors being formed utilizing an image sensor wafer, the image sensor wafer comprising a substrate and a sensor layer formed over the substrate, the method comprising the steps of:

forming backside trenches in a backside surface of the sensor layer;

implanting a dopant into the sensor layer through the backside trenches so as to form backside field isolation implant regions corresponding to the backside trenches;

filling the backside trenches;

forming at least one antireflective layer over the filled backside trenches; and

further processing the image sensor wafer to form the plurality of image sensors.

2. The method of claim 1 wherein the image sensor wafer comprises a silicon-on-insulator (SOI) wafer having a buried oxide layer arranged between the substrate and the sensor layer.

3. The method of claim 1 wherein the image sensor wafer comprises an epitaxial wafer having a P−

sensor layer formed over a P+ substrate.

4. The method of claim 1 farther comprising the steps of:

forming an oxide layer over the sensor layer;

forming a nitride layer over the oxide layer;

forming alignment marks that extend through the oxide and nitride layers and into the sensor layer.

5. The method of claim 4 wherein the step of forming backside trenches in the backside surface of the sensor layer further comprises the step of etching the backside trenches through the nitride and oxide layers.

6. The method of claim 1 further comprising the step of forming a liner oxide layer within the backside trenches.

7. The method of claim 1 wherein the step of filling the backside trenches comprises filling the backside trenches with one of oxide and polysilicon.

8. The method of claim 7 wherein the step of forming at least one antireflective layer over the filled backside trenches on the backside surface of the sensor layer further comprises the steps of:

forming an antireflective oxide layer on the backside surface of the sensor layer; and

forming an antireflective nitride layer over the antireflective oxide layer.

9. The method of claim 8 farther comprising the step of performing a passivation implant operation in conjunction with the formation of the antireflective oxide layer.

10. The method of claim 8 wherein the antireflective oxide layer has a thickness of approximately 50 Angstroms and the antireflective nitride layer has a thickness of approximately 500 Angstroms.

11. The method of claim 1 further comprising the steps of:

depositing a photoresist over the antireflective layer;

patterning the photoresist to form openings over the backside trenches; and

implanting a dopant through the openings to form backside well isolation implant regions corresponding to the backside trenches.

12. The method of claim 1 wherein the step of further processing the image sensor wafer to form the plurality of image sensors further comprises the steps of:

forming an oxide layer over said at least one antireflective layer;

attaching a temporary carrier wafer to a backside surface of the oxide layer;

removing the substrate;

forming photosensitive elements of the pixel arrays in the sensor layer;

forming frontside trenches in a frontside surface of the sensor layer;

forming frontside field isolation implant regions corresponding to the frontside trenches;

filling the frontside trenches;

forming frontside well isolation implant regions corresponding to the frontside trenches;

forming at least one dielectric layer on the frontside surface of the sensor layer;

attaching a handle wafer to a frontside surface of said at least one dielectric layer;

removing the temporary carrier wafer; and

separating the image sensor wafer into the plurality of image sensors.

13. The method of claim 12 wherein said at least one dielectric layer comprises an interlayer dielectric and further comprises an intermetal dielectric separating multiple levels of metallization.

14. An image sensor having a pixel array configured for backside illumination, comprising:

a sensor layer comprising a plurality of photosensitive elements of the pixel array;

an oxide layer adjacent a backside surface of the sensor layer; and

at least one dielectric layer adjacent a frontside surface of the sensor layer;

wherein the sensor layer comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements, said backside trenches having corresponding backside field isolation implant regions formed in the sensor layer.

15. The image sensor of claim 14 farther comprising at least one antireflective layer arranged between the oxide layer and the sensor layer.

16. The image sensor of claim 14 wherein the sensor layer further comprises a plurality of frontside trenches formed in the frontside surface of the sensor layer and arranged between respective pairs of the photosensitive elements in alignment with corresponding ones of the backside trenches, said frontside trenches having corresponding frontside field isolation implant regions formed in the sensor layer.

17. The image sensor of claim 16 wherein the backside trenches have corresponding backside well isolation implant regions formed in the sensor layer in alignment with the backside trenches and the frontside trenches have corresponding frontside well isolation implant regions formed in the sensor layer in alignment with the frontside trenches.

18. The image sensor of claim 14 wherein said image sensor comprises a CMOS image sensor.

19. A digital imaging device comprising:

an image sensor having a pixel array configured for backside illumination; and

one or more processing elements configured to process outputs of the image sensor to generate a digital image;

wherein said image sensor comprises;

a sensor layer comprising a plurality of photosensitive elements of the pixel array;

an oxide layer adjacent a backside surface of the sensor layer; and

at least one dielectric layer adjacent a frontside surface of the sensor layer;

wherein the sensor layer comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements, said backside trenches having corresponding backside field isolation implant regions formed in the sensor layer.

20. The digital imaging device of claim 19 wherein said imaging device comprises a digital camera.