Charge Balance Techniques for Power Devices

• US 20100006927A1
• Filed: 09/17/2009
• Published: 01/14/2010
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Christopher Boguslaw Kocon
• Inventors: Kocon, Christopher Boguslaw
• Granted Patent: US 7,936,013 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die.

Claims

1. A vertically-conducting charge balance semiconductor power device, comprising:

an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state;

a non-active perimeter region surrounding the active area, wherein no current flows along the vertical dimension through the non-active perimeter region when the plurality of cells are biased in the conducting state; and

strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p pillars having a depth extending along the vertical dimension, a width, and a length, the strips of p and n pillars extending through both the active area and the non-active perimeter region along a length of a die containing the semiconductor power device, the length of the die extending parallel to the length of the strips of p pillars, each of the strips of p pillars including a plurality of discontinuities forming portions of a plurality of strips of n regions, the plurality of strips of n regions extending in the non-active perimeter region perpendicular to the length of the die.

2. The vertically-conducting charge balance semiconductor power device of claim 1 wherein an outer one of the plurality of strips of n regions has a width greater than a width of an inner one of the plurality of strips of n regions.

3. The vertically-conducting charge balance semiconductor power device of claim 1 further comprising a field plate in the non-active perimeter region.

4. The vertically-conducting charge balance semiconductor power device of claim 1 wherein the non-active perimeter region comprises a plurality of p type rings extending around the active area.

5. The vertically-conducting charge balance semiconductor power device of claim 4 wherein a spacing between adjacent p type rings progressively increases in the direction away from the active area.

6. The vertically-conducting charge balance semiconductor power device of claim 4 wherein the plurality of p type rings are floating rings.

7. The vertically-conducting charge balance semiconductor power device of claim 1 further comprising a field plate conductor extending into the non-active perimeter region, wherein a portion of the field plate conductor is insulated from underlying strips of p and n pillars by a dielectric layer.

8. The vertically-conducting charge balance semiconductor power device of claim 1 further comprising:

p type body regions extending over strips of p pillars;

gate electrodes extending adjacent the body regions; and

n type source regions in the body regions.