RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

• US 20100006995A1
• Filed: 01/24/2008
• Published: 01/14/2010
• Est. Priority Date: 01/30/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Haga, Motoharu, Kasuya, Yasumasa, Yasunaga, Shoji
• Granted Patent: US 8,039,934 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/27013 for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49537 : Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49555 : the bent parts being the outer leads
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/564 : Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device comprises a semiconductor chip including a silicon substrate, a die pad to which the semiconductor chip is secured through a first solder layer, a resin-encapsulating layer encapsulating the semiconductor chip, and lead terminals electrically connected to the semiconductor chip and including inner lead portion covered with the resin-encapsulating layer. The lead terminals are made of copper or a copper alloy. The die pad is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals.

Claims

1. A resin-sealed semiconductor device comprising:

a semiconductor chip including a silicon substrate;

a die pad on which the semiconductor chip is secured via a solder layer;

a sealing resin layer sealing the semiconductor chip; and

a plurality of lead terminals connected electrically with the semiconductor chip, one end portions of the plurality of lead terminals being covered with the sealing resin layer,

wherein the lead terminals are formed of copper or a copper alloy, and

wherein the die pad is formed of a 42 alloy or a Kovar alloy, the die pad being formed with a thickness equal to or less than a thickness of the lead terminals.

4. The resin-sealed semiconductor device according to claim 1,

wherein the semiconductor chip is secured on one main surface of the die pad, and

wherein the die pad is disposed such that the other main surface of the die pad opposite from the one main surface thereof is exposed through the sealing resin layer.

5. The resin-sealed semiconductor device according to claim 1,

wherein, in the die pad, in a corner part formed by the other main surface and a side surface, a cut-off portion is provided.

6. The resin-sealed semiconductor device according to claim 5,

wherein the die pad is quadrangular as seen in a plan view, and

wherein the cut-off portion is provided one in each of four corner parts formed by the other main surface of the die pad and side surfaces of the die pad.

7. The resin-sealed semiconductor device according to claim 1,

wherein the die pad has a plan area larger than a plan area of the semiconductor chip, and

wherein, in the die pad, in a predetermined region other than a region to which the semiconductor chip is secured, an open part that penetrates from one main surface side to the other main surface side of the die pad is provided.

8. The resin-sealed semiconductor chip according to claim 7,

wherein, as the open part, a plurality of open parts are so provided as to surround the semiconductor chip, as seen in a plan view.

2. A resin-sealed semiconductor device comprising:

a semiconductor chip including a silicon substrate;

a die pad on which the semiconductor chip is secured via a solder layer;

a sealing resin layer sealing the semiconductor chip; and

a plurality of lead terminals connected electrically with the semiconductor chip, one end portion of the plurality of lead terminals being covered by the sealing resin layer,

wherein the die pad and the lead terminals are formed of copper and a copper alloy, the die pad being formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

3. The resin-sealed semiconductor device according to claim 2, wherein the die pad is formed with a thickness larger than the thickness of the lead terminals, which is a thickness of 0.5 mm or more.

9. The resin-sealed semiconductor device according to claim 2,

wherein the semiconductor chip is secured on one main surface of the die pad, and

wherein the die pad is disposed such that the other main surface of the die pad opposite from the one main surface thereof is exposed through the sealing resin layer.

10. The resin-sealed semiconductor device according to claim 2,

wherein, in the die pad, in a corner part formed by the other main surface and a side surface, a cut-off portion is provided.

11. The resin-sealed semiconductor device according to claim 2,

wherein the die pad has a plan area larger than a plan area of the semiconductor chip, and

wherein, in the die pad, in a predetermined region other than a region to which the semiconductor chip is secured, an open part that penetrates from one main surface side to the other main surface side of the die pad is provided.

12. A method of manufacturing a resin-sealed semiconductor device, comprising:

a step of forming a lead frame including a lead terminal;

a step of forming a die pad as a separate piece from the lead frame;

a step of securing a semiconductor chip including a silicon substrate, via a solder layer, on one main surface of the die pad; and

a step of resin-sealing at least the semiconductor chip with a sealing resin layer,

wherein the step of forming the lead frame comprises a step of forming the lead frame with copper or a copper alloy, and

wherein the step of forming the die pad comprises a step of forming the die pad with a 42 alloy or a Kovar alloy and a step of forming the die pad with a thickness equal to or less than a thickness of the lead frame.

15. The method of manufacturing a resin-sealed semiconductor device according to claim 12, further comprising, after the step of securing the semiconductor chip on the die pad:

a step of joining the die pad on which the semiconductor chip is secured to a predetermined position on the lead frame.

13. A method of manufacturing a resin-sealed semiconductor device, comprising:

a step of forming a lead frame including a lead terminal;

a step of forming a die pad as a separate piece from the lead frame;

a step of securing a semiconductor chip including a silicon substrate, via a solder layer, on one main surface of the die pad; and

a step of resin-sealing at least the semiconductor chip with a sealing resin layer,

wherein the step of forming the lead frame comprises a step of forming the lead frame with copper or a copper alloy, and

wherein the step of forming the die pad comprises a step of forming the die pad with copper and a copper alloy and a step of forming the die pad with a thickness larger than a thickness of the lead frame, which is a thickness of 0.25 mm or more.

14. The method of manufacturing a resin-sealed semiconductor device according to claim 13,

wherein the step of forming the die pad comprises a step of forming the die pad with a thickness larger than the thickness of the lead frame, which is a thickness of 0.5 mm or more.

16. The method of manufacturing a resin-sealed semiconductor device according to claim 13, further comprising, after the step of securing the semiconductor chip on the die pad:

a step of joining the die pad on which the semiconductor chip is secured to a predetermined position on the lead frame.