Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection

• US 20100007019A1
• Filed: 09/18/2009
• Published: 01/14/2010
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Pendse, Rajendra D.
• Granted Patent: US 8,076,232 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/29109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/484 : Connecting portions
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/75301 : Bonding head
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83856 : Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/83907 : Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

providing a substrate;

forming a plurality of traces on the substrate, each trace having an interconnect site with edges parallel to the trace from a plan view for increasing escape routing density; and

forming a plurality of composite interconnects between the interconnect sites and bump pads on the semiconductor die, each composite interconnect having a non-fusible portion connected to the bump pad on the semiconductor die and fusible portion connected to the interconnect site on the substrate.

2. The method of claim 1, wherein the non-fusible portion of the composite interconnect includes gold, copper, nickel, lead solder, or lead-tin alloy.

3. The method of claim 1, wherein the fusible portion of the composite interconnect includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead.

4. The method of claim 1, wherein the composite interconnect is tapered.

5. The method of claim 4, wherein the tapered composite interconnect reduces stress and damage to the semiconductor die.

6. The method of claim 1, further including depositing an underfill material between the semiconductor die and substrate.

7. The method of claim 1, further including forming a finish over the substrate.

8. A method of making a semiconductor device, comprising:

providing a semiconductor die;

providing a substrate having a trace; and

forming a composite interconnect between the trace and a bump pad on the semiconductor die, the composite interconnect having a non-fusible portion connected to the bump pad on the semiconductor die and a fusible portion connected to the trace on the substrate.

9. The method of claim 8, wherein the non-fusible portion of the composite interconnect includes gold, copper, nickel, lead solder, or lead-tin alloy.

10. The method of claim 8, wherein the fusible portion of the composite interconnect includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead.

11. The method of claim 8, wherein the composite interconnect is tapered.

12. The method of claim 11, wherein the tapered composite interconnect reduces stress and damage to the semiconductor die.

13. The method of claim 8, wherein a width of the interconnect site under the composite interconnect is no greater than a width of the trace away from the composite interconnect.

14. The method of claim 8, wherein the interconnect site has a width less than 1.2 times a width of the trace.

15. A method of making a semiconductor device, comprising:

providing a semiconductor die;

providing a substrate having a trace;

forming a composite bump material over an interconnect site on the trace or a bump pad on the semiconductor die, the composite bump material having a fusible portion and non-fusible portion; and

reflowing the composite bump material to form a composite interconnect between the interconnect site on the substrate and bump pad on the semiconductor die.

16. The method of claim 15, wherein the non-fusible portion of the composite interconnect includes gold, copper, nickel, lead solder, or lead-tin alloy.

17. The method of claim 15, wherein the fusible portion of the composite interconnect includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead.

18. The method of claim 15, wherein the composite interconnect is tapered.

19. The method of claim 15, further including:

forming the fusible portion of the composite bump material adjacent to the interconnect site on the trace; and

forming the non-fusible portion of the composite bump material adjacent to the bump pad on the semiconductor die.

20. A semiconductor device, comprising:

a semiconductor die;

a substrate having a trace; and

a composite interconnect formed between an interconnect site on the trace and a bump pad on the semiconductor die, the composite interconnect having a non-fusible portion connected to the bump pad and fusible portion connected to the trace.

21. The semiconductor die of claim 20, wherein the non-fusible portion of the composite interconnect includes gold, copper, nickel, lead solder, or lead-tin alloy.

22. The semiconductor die of claim 20, wherein the fusible portion of the composite interconnect includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead.

23. The semiconductor die of claim 20, wherein the composite interconnect is tapered.

24. The semiconductor die of claim 20, wherein the fusible portion of the composite interconnect is adjacent to the interconnect site on the trace, and the non-fusible portion of the composite interconnect is adjacent to the bump pad on the semiconductor die.

25. The semiconductor die of claim 20, wherein the interconnect site has edges parallel to the trace.