Semiconductor device, method for manufacturing semiconductor device, method for manufacturing semiconductor package

• US 20100007030A1
• Filed: 07/08/2009
• Published: 01/14/2010
• Est. Priority Date: 07/10/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Kadogawa, Yutaka, Koike, Osamu
• Granted Patent: US 9,892,968 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/14636 Interconnect structures

Abstract

There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting said active area;

at least one electrode pad electrically connected to any of said active elements; and

at least one Through Silicon VIA electrode electrically connected to said electrode pad by way of said non-active area, wherein

said non-active area has an insulating region obtained by forming an insulating film on said semiconductor substrate, and a dummy section obtained by leaving a base material of said semiconductor substrate in said insulating region, and

an outer edge of said Through Silicon VIA electrode does not intersect with the boundary between said insulating region and said dummy section.

2. The semiconductor device of claim 1, wherein said dummy section is provided in said non-active area only on the outside of the region through which said Through Silicon VIA electrode passes.

3. The semiconductor device of claim 2, further comprising a ring-shaped dummy section for surrounding the region through which said Through Silicon VIA electrode passes.

4. The semiconductor device of claim 1, wherein said dummy section is provided in said non-active area outside and inside the region through which said Through Silicon VIA electrode passes.

5. The semiconductor device of claim 1, wherein a dummy section that extends over the entire surface of the region through which said Through Silicon VIA electrode passes is formed in said non-active area.

6. The semiconductor device of claim 1, wherein said dummy section includes a plurality of island-shaped dummy section uniformly disposed inside said insulating region.

7. The semiconductor device of claim 1, wherein said semiconductor substrate includes a plurality of imaging elements formed in said active area, and the area in which said Through Silicon VIA electrode is formed is present inside a non-active area that extends outside of said imaging elements.

13. A method for manufacturing a semiconductor package that includes the semiconductor device of claim 1, comprising:

a step for forming a Through Silicon VIA hole from the reverse surface of said semiconductor substrate to said electrode pad in a Through Silicon VIA electrode formation area of said semiconductor substrate;

a step for forming an insulating film on an inner wall of said Through Silicon VIA hole and the reverse surface of said semiconductor substrate;

a step for selectively removing said insulating film of the bottom surface of said Through Silicon VIA hole and exposing said electrode pad inside said Through Silicon VIA hole;

a step for sequentially forming a barrier metal and an electroconductive film for covering the reverse surface of said semiconductor substrate and the inner wall of said Through Silicon VIA hole to form said Through Silicon VIA electrode and reverse surface wiring electrically connected to said Through Silicon VIA electrode on the reverse surface of said semiconductor substrate;

a step for forming an insulating film having an aperture on the reverse surface of said semiconductor substrate; and

a step for forming an external terminal on the exposed portion of said reverse surface wiring through said aperture.

8. A method for manufacturing a semiconductor device, comprising:

a step for forming, on a semiconductor substrate, an active area in which a plurality of active elements are formed, and a non-active area excepting said active area;

a step for forming at least one electrode pad electrically connected to any of said active elements; and

a step for forming at least one Through Silicon VIA electrode electrically connected to said electrode pad by way of said non-active area, wherein

the step for forming said non-active area includes a step for forming a dummy section obtained by leaving a base material of said semiconductor substrate in an insulating region composed of an insulating film; and

said Through Silicon VIA electrode is formed such that an outer edge of thereof does not intersect with the boundary between said insulating region and said dummy section.

9. The method for manufacturing a semiconductor device of claim 8, wherein the step for forming said non-active area includes a step for providing said dummy section in only the outside of the region through which said Through Silicon VIA electrode passes.

10. The method for manufacturing a semiconductor device of claim 8, further comprising a step for providing a ring-shaped dummy section for surrounding the region through which said Through Silicon VIA electrode passes.

11. The method for manufacturing a semiconductor device of claim 8, wherein the step for forming said non-active area includes a step for providing said dummy section outside and inside the region through which said Through Silicon VIA electrode passes.

12. The method for manufacturing a semiconductor device of claim 8, wherein the step for forming said non-active area includes a step for forming a dummy section that extends over the entire surface of the region through which said Through Silicon VIA electrode passes.