Memory Device And Method For Making Same
First Claim
Patent Images
1. A memory cell, comprising:
- a programmable resistance memory element; and
a heterojunction bipolar transistor electrically coupled to said memory element.
1 Assignment
0 Petitions
Accused Products
Abstract
An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor.
28 Citations
25 Claims
-
1. A memory cell, comprising:
-
a programmable resistance memory element; and a heterojunction bipolar transistor electrically coupled to said memory element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A memory array, comprising:
a plurality of memory cells, each of said cells comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor. - View Dependent Claims (15, 16, 17, 18, 19)
-
20. A method of forming a memory array, comprising:
-
forming a buried layer over a substrate; forming a collector layer over said buried layer; forming spacedly disposed collector regions by introducing first insulating trenches through said collector layer; forming a base layer over said collector regions and over said first insulating trenches; forming spacedly disposed base strips by introducing second insulating trenches through said base layer; forming spacedly disposed emitter regions over first portions of said base strips overlying said collector regions; and forming memory elements over said emitter regions. - View Dependent Claims (21, 22, 23, 24, 25)
-
Specification