Multiple series passive element matrix cell for three-dimensional arrays

• US 20100008123A1
• Filed: 07/09/2008
• Published: 01/14/2010
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 8,014,185 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of forming a nonvolatile memory cell is also described.

Claims

1. A nonvolatile memory cell, comprising:

at least two two-terminal non-linear steering elements arranged in series; and

a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements.

2. A memory array, comprising:

a plurality of nonvolatile memory cells of claim 1;

a plurality of word lines; and

a plurality of bit lines.

3. The memory array of claim 2, wherein each nonvolatile memory cell comprises:

a first terminal connected to one of the plurality of bit lines;

a second terminal connected to one of the plurality of word lines; and

the resistivity switching storage element and the at least two two-terminal non-linear steering elements are arranged in series between the first terminal and the second terminal.

4. The memory array of claim 2, wherein each of the at least two two-terminal non-linear switching elements comprises a diode.

5. The memory array of claim 4, wherein each diode comprises a semiconductor p-n diode or a semiconductor p-i-n diode.

6. The memory array of claim 4, wherein each diode comprises a metal-insulator-metal (MIM) diode or a metal-insulator-insulator-metal (MIIM) diode.

7. The memory array of claim 2, wherein the resistivity switching storage element is selected from at least one of antifuse, fuse, polysilicon memory effect element, metal oxide or switchable complex metal oxide element, carbon based element, phase change material element, conductive bridge element, or switchable polymer element.

8. The memory array of claim 7, wherein the resistivity switching storage element comprises the carbon based element.

9. The memory array of claim 8, wherein the carbon based element is selected from carbon nanotube, amorphous carbon, microcrystalline carbon, graphite or graphene resistivity switching material.

10. The memory array of claim 9, wherein the resistivity switching storage element has a thickness in a range of about 2 to about 10 Å

.

11. The memory array of claim 2, wherein the at least two non-linear steering elements comprise two non-linear steering elements.

12. The memory array of claim 11, wherein the resistivity switching storage element is arranged between the two non-linear steering elements.

13. The memory array of claim 12, wherein the resistivity switching storage element is arranged on one side of both of the two non-linear steering elements.

14. The memory array of claim 2, wherein the at least two non-linear steering elements comprises four non-linear steering elements arranged in series.

15. The memory array of claim 14, wherein:

the four non-linear steering elements comprise a first pair of non-linear steering elements and a second pair of non-linear steering elements; and

the resistivity switching storage element is arranged between the first pair and the second pair of non-linear steering elements.

16. The memory array of claim 14, wherein the resistivity switching storage element is arranged on one side of the four non-linear steering elements.

17. The memory array of claim 14, wherein:

the four non-linear steering elements comprise a first pair of non-linear steering elements and a second pair of non-linear steering elements;

a first conductor element is arranged between the non-linear steering elements of the first pair; and

a second conductor element is arranged between the non-linear steering elements of the second pair.

18. The memory cell of claim 1, wherein the at least two two-terminal non-linear steering elements and the resistivity switching storage element are arranged vertically between a lower electrode and an upper electrode.

19. The memory array of claim 2, wherein the plurality of nonvolatile memory cells, word lines and bit lines are arranged to comprise a monolithic three dimensional memory array.

20. A method of forming a memory cell, comprising:

forming a lower electrode;

forming at least two two-terminal non-linear steering elements arranged in series and a resistivity switching storage element over the lower electrode; and

forming an upper electrode over the least two two-terminal non-linear steering elements and the resistivity switching storage element.

21. The method of claim 20, wherein each the at least two non-linear switching elements each comprises a diode.

22. The method of claim 21, wherein each diode is formed at a temperature below about 600°

C.

23. The method of claim 21, wherein:

each diode comprises a MIM diode, a MIIM diode or a semiconductor diode; and

the resistivity switching storage element is selected from at least one of antifuse, fuse, polysilicon memory effect element, metal oxide or switchable complex metal oxide element, carbon based element, phase change material element, conductive bridge element, or switchable polymer element.