Memory devices having volatile and non-volatile memory characteristics and methods of operating the same

• US 20100008139A1
• Filed: 07/08/2009
• Published: 01/14/2010
• Est. Priority Date: 07/08/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Bae, Dong-Il
• Granted Patent: US 8,169,823 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells

Abstract

Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode and a charge trap layer between the floating body and the gate electrode, where first bit data is written in one of the charge trap layer and the floating body, and second bit data is written in one of the charge trap layer and the floating body in which first bit data is not written.

Claims

1. A method of writing data to a semiconductor memory device, the semiconductor memory device including a floating body on a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode, and a charge trap layer between the floating body and the gate electrode, the method comprising:

writing a first bit to the charge trap layer; and

writing a second bit to the floating body.

2. The method of claim 1, wherein the writing a first bit includes at least one of trapping a charge in the charge trap layer and erasing a charge from the charge trap layer.

3. The method of claim 2, wherein the trapping a charge in the charge trap layer includes applying a gate programming voltage to the gate electrode,

applying a drain programming voltage to the drain region, and

applying a lower voltage than the drain programming voltage to the source region.

4. The method of claim 2, wherein the trapping a charge in the charge trap layer includes applying a gate programming voltage to the gate electrode, and

grounding the drain and source regions.

5. The method of claim 1, wherein the writing a second bit includes at least one of storing holes in the floating body and erasing holes from the floating body.

6. The method of claim 5, wherein the storing holes in the floating body includes applying a gate programming voltage to the gate electrode,

applying a drain programming voltage to the drain region, and

applying a lower voltage than the drain programming voltage to the source region.

7. The method of claim 5, wherein the erasing holes from the floating body includes applying a positive gate voltage to the gate electrode,

a negative erasing voltage to the drain region, and

grounding the source region.

8. The method of claim 5, wherein the storing holes in the floating body includes applying voltages to the source region, the floating body and the drain region so that the source region is forward biased with respect to the floating body and the drain region is reverse biased with respect to the floating body, so that holes accumulate in a channel region, and

applying a negative voltage to the gate electrode and grounding the source and drain regions, so that accumulated holes are maintained in the channel region.

9. The method of claim 8, wherein the erasing holes from the floating body includes applying voltages to the source region, the floating body and the drain region to lower a voltage barrier of the source region and the floating body, so that holes are removed from the channel region;

and

applying a negative voltage to the gate electrode and grounding the source and drain region.

10. A method of reading multi-bit data in a multi-bit semiconductor memory device, the multi-bit semiconductor device including a floating body on a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode, and a charge trap layer between the floating body and the gate electrode, the method comprising:

applying a read gate voltage to the gate electrode;

applying a read drain voltage to the drain region;

applying a read source voltage that is lower than the read drain voltage to the source region; and

outputting multi-bit data by comparing a drain current with reference currents.

11. A method of claim 10, wherein the reference currents include a first reference current for determining a least significant bit (LSB) data state of the memory,

a second reference current, and

a third reference current, one or more of the second and third reference currents for determining a most significant bit (MSB) data state of the memory.

12. The method of claim 10, wherein the first reference current has a value between a first read drain current corresponding to a LSB data of “

0” and

a second read drain current corresponding to a LSB of “

1”

,

the second reference current has a value between the second read drain current and a third read drain current, the third read drain current corresponding to a MSB of “

1” and

a LSB of “

1”

,

the third reference current has a value between the first read drain current and a fourth read drain current, the fourth read drain current corresponding to a MSB of “

0” and

a LSB of “

0”

, and

the first through fourth read drain currents are drain currents when a reading voltage is applied to the gate electrode.

13. The method of claim 12, wherein the outputting multi-bit data includes determining the LSB by comparing the drain current with the first reference current, and

determining the MSB by one of comparing the drain current with the second reference current when the LSB is a “

1” and

comparing the drain current with the third reference current when the LSB is a “

0”

.

14. A method of reading data in a semiconductor memory device, the semiconductor memory device including a floating body on a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode, and a charge trap layer between the floating body and the gate electrode, the method comprising:

applying a read drain voltage to the drain region,

applying a read source voltage lower than the read drain voltage to the source region;

sequentially applying reference voltages to the gate electrode; and

outputting multi-bit data of the memory by determining whether or not a drain current flows at one or more of the reference voltages.

15. The method of claim 14, wherein the reference voltages include a first reference voltage for determining a least significant bit (LSB) data state of the memory,

a second reference voltage, and

and a third reference voltage, one or more of the second and third reference voltages for determining a most significant bit (MSB) data state of the memory.

16. The method of claim 14, wherein the first reference voltage has a value between a first threshold voltage corresponding to a LSB of “

0” and

a MSB of “

1” and

a second threshold voltage corresponding to a LSB of “

1” and

MSB of “

0”

,

the second reference voltage has a value between the second threshold voltage and a third threshold voltage corresponding to a MSB of “

1 ” and

a LSB of “

1”

, and

the third reference voltage has a value between the first threshold voltage and a fourth threshold voltage, the fourth threshold voltage corresponding to a MSB of “

0” and

a LSB of “

0”

.

17. The method of claim 16, wherein the outputting multi-bit data of the memory includes determining the LSB according to whether or not a drain current flows when the first reference voltage is applied to the gate electrode, and

determining the MSB according to one of whether or not a drain current flows when the second reference voltage is applied to the gate electrode if the LSB is a “

1” and

whether or not a drain current flows when the third reference voltage is applied to the gate electrode if the LSB is a “

0”

.

18. A method of reading data in a semiconductor memory device, the semiconductor memory device including a floating body on a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode, and a charge trap layer between the floating body and the gate electrode, the method comprising:

applying a read drain voltage to the drain region,

applying a read source voltage lower than the read drain voltage to the source region;

applying a reference voltage to the gate electrode and determining a least significant bit (LSB) data state of the memory based on whether or not a first drain current flows;

applying one of a first read gate voltage to the gate electrode if the LSB is a “

1” and

determining a most significant bit (MSB) data state of the memory by comparing a second drain current that is output when applying the first read gate voltage with a first reference current and a second read gate voltage to the gate electrode if the LSB is a “

0” and

determining the MSB data state of the memory by comparing a third drain current that is output when applying the second read gate voltage with a second reference current.

19. The method of claim 18, wherein the first reference current has a value between that of a drain current corresponding to a MSB of “

0” and

a LSB of “

1”

when the first read gate voltage is applied to the gate electrode and a drain current corresponding to a MSB of “

1 ” and

a LSB of “

1 ”

when the first read gate voltage is applied to the gate electrode.

20. The method of claim 19, wherein the second reference current has a value between that of a drain current corresponding to a MSB of “

0” and

a LSB of “

0”

when the second read gate voltage is applied to the gate electrode and a drain current corresponding to a MSB of “

1” and

a LSB of “

0”

when the second read gate voltage is applied to the gate electrode.