NONVOLATILE MEMORY DEVICES SUPPORTING MEMORY CELLS HAVING DIFFERENT BIT STORAGE LEVELS AND METHODS OF OPERATING THE SAME

• US 20100008140A1
• Filed: 06/10/2009
• Published: 01/14/2010
• Est. Priority Date: 07/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hyun
• Granted Patent: US 8,144,505 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Nonvolatile memory devices include a memory cell array including a first memory cell and an adjacent second memory cell and a data input/output circuit configured to operate the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not equal to n. The first and second memory cells may be adjacent cells connected to same word line or to the same bit line. The memory cell array may include a third memory cell adjacent the first memory cell and the data input/output circuit may be further configured to operate the third memory cell as a k-bit cell. The first and second memory cells may be connected to the same word line and the first and third memory cells may be connected to the same bit line. The data input/output circuit may be configured to operate the first memory cell as a j-bit cell responsive to detecting a number of erase operations for the first memory cell meeting a predetermined criterion, wherein j is less than n. In some embodiments, j may be equal to m.

Claims

1. A nonvolatile memory device comprising:

a memory cell array comprising a first memory cell and an adjacent second memory cell; and

a data input/output circuit configured to operate the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not equal to n.

2. The device of claim 1, wherein the first and second memory cells are connected to same word line or to the same bit line.

3. The device of claim 1, wherein the memory cell array comprises a third memory cell adjacent the first memory cell and wherein the data input/output circuit is further configured to operate the third memory cell as a k-bit cell.

4. device of claim 3, wherein the first and second memory cells are connected to the same word line and wherein the first and third memory cells are connected to the same bit line.

5. The device of claim 4, wherein m is greater than n.

6. The device of claim 5, wherein k is equal to n.

7. The device of claim 4, wherein the data input/output circuit is configured to complete programming of the third memory cell before programming a final bit of the first memory cell in a memory block write operation.

8. The device of claim 4, wherein the data input/output circuit is configured to complete programming of the second and third memory cells before programming a final bit of the first memory cell in a memory block write operation.

9. The device of claim 1, wherein the data input/output circuit is configured to complete programming of the second memory cell before programming a final bit of the first memory cell in a memory block write operation.

10. The device of claim 1, wherein m is equal to 1 and wherein n is equal to 2.

11. The device of claim 10, wherein the data input/output circuit is configured to pre-program the second memory cell before programming a first bit for the first memory cell and to re-program the second memory cell after programming the first bit for the first memory cell.

12. The device of claim 1, wherein the data input/output circuit is configured to operate the first memory cell as a j-bit cell responsive to detecting a number of erase operations for the first memory cell meeting a predetermined criterion, wherein j is less than n.

13. The device of claim 12, wherein j is equal to m.

14. A method of operating a nonvolatile memory device comprising a memory cell array comprising a first memory cell and an adjacent second memory cell, the method comprising:

operating the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not equal to n.

15. The method of claim 14, further comprising completing programming of the second memory cell before programming a final bit of the first memory cell in a memory block write operation.

16. The method of claim 14, wherein m is equal to 1 and wherein n is equal to 2.

17. The method of claim 16, further comprising:

pre-programming the second memory cell;

programming a first bit for the first memory cell after pre-programming the second memory cell; and

re-programming the second memory cell after programming the first bit for the first memory cell.

18. The method of claim 14, further comprising operating the first memory cell as a j-bit cell responsive to detecting a number of erase operations for the first memory cell meeting a predetermined criterion, wherein j is less than n.

19. The method of claim 18, wherein j is equal to m.

20. A computing system comprising:

a nonvolatile memory device comprising a memory cell array comprising a first memory cell and an adjacent second memory cell and a data input/output circuit configured to operate the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not equal to n; and

a host configured to use the nonvolatile memory device as a storage unit.