SWITCHING ARCHITECTURE WITH PACKET ENCAPSULATION

• US 20100008357A1
• Filed: 02/06/2009
• Published: 01/14/2010
• Est. Priority Date: 05/03/2002
• Status: Active Grant

• Current Assignee: Ribbon Communications Operating Company, Inc. (Ribbon Communications, Inc.)
• Original Assignee: Cedar Point Communications Incorporated
• Inventors: Miller, Paul, English, Daniel W., Saab, Hicham, Doucette, John
• Granted Patent: US 8,773,996 B2
• Time in Patent Office: Days
• US Class Current: 370/356
• CPC Class Codes: H04J 3/16 in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted H04J3/17, H04J3/24 take precedence
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/6459 Multiplexing, e.g. TDMA, CDMA
• CPC Class Codes: H04L 2012/6475 N-ISDN, Public Switched Telephone Network [PSTN]
• CPC Class Codes: H04L 2012/6489 Buffer Management, Threshold setting, Scheduling, Shaping
• CPC Class Codes: H04M 7/0003 Interconnection between telephone networks and data networks
• CPC Class Codes: H04M 7/0075 Details of addressing, directories or routing tables
• CPC Class Codes: H04M 7/0078 Security; Fraud detection; Fraud prevention
• CPC Class Codes: H04M 7/1215 where a cable TV network is used as an access to the PSTN/ISDN
• CPC Class Codes: H04M 7/128 Details of addressing, directories or routing tables

Abstract

The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.

Claims

1. A system for passing TDM traffic through a packet switch, comprising

a packet switch having a plurality of data ports and being capable of routing FSDU packets between the plurality of data ports;

a TDM encapsulation circuit coupled to a data flow of TDM data and having a circuit demultiplexer for processing an incoming data flow of TDM data to buffer data associated with different TDM circuits into different buffer locations,

a timer for monitoring a frame boundary, and

a FSDU generator for generating an FSDU and filling the generated FSDU with data associated with a respective one of the TDM circuits and for generating header information representative of information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits.

2. A system according to claim 1, further comprising

a merge circuit for merging the generated FSDU with packet flow data being sent to the packet switch.

3. A system according to claim 1, further comprising

a decapsulation circuit for processing a generated FSDU passed through the packet switch to provide data to one or more TDM circuits sending data from a port of the packet switch.

4. A system according to claim 1, wherein

the circuit demultiplexer includes means for accessing a connection table having information representative of the ports associated with a circuit.

5. A system according to claim 1, further including

a priority switch for associating a routing priority level with a generated FSDU.

6. A system according to claim 5, further comprising

a bandwidth allocation process for allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing traffic through the packet switch.

7. A system according to claim 1, further comprising

a jitter buffer for reducing variable delays arising from passing through the packet switch.

8. A system according to claim 7, wherein

the jitter buffer has a size selected as a function of a minimum and maximum latency for data passing through the packet switch.

9. A system according to claim 7, wherein

the jitter buffer has a size selected to maintain jitter below 125 microseconds.

10. A system according to claim 1, wherein

the packet switch includes ports capable of supporting a combination of traffic types.

11. A system according to claim 1, wherein

traffic types include packet type traffic and TDM type traffic.

12. A system according to claim 1, further comprising

a dropped-circuit detector for detecting a dropped TDM circuit.

13. A system according to claim 12, wherein

the FSDU generator responds to the dropped-circuit detector to adjust the contents of the FSDU.

14. A process for passing TDM traffic through a packet switch, comprising

providing a packet switch having a plurality of data ports and being capable of routing FSDU packets between the plurality of data ports;

identifying a TDM data flow,

encapsulating the TDM data flow by sorting the TDM data flow into different respective buffer locations,

generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits,

generating header information representative of information for routing the generated FSDU to a port associated with the respective one of the TDM circuits, and

combining the generated FSDU with a flow of packet data being sent to the packet switch.

15. A process according to claim 14, further comprising

processing a generated FSDU having been passed through the packet switch to reconstruct a TDM data flow circuit at an output port of the packet switch.

16. A process according to claim 15, further comprising

monitoring the number of TDM circuits within the TDM data flow to identify a change in the number of TDM circuits.

17. A process according to claim 16, further comprising

altering the contents of the generated FSDU as a function of a detected change in the number of circuits in the TDM data flow.

18. A process according to claim 14, further comprising

setting a timer to establish a time period for filling the generated FSDU.

19. A process according to claim 18, wherein

the time period is set to the TDM frame boundary period.

20. A process according to claim 14, further comprising

buffering a generated TDM circuit at an output port to reduce latency induced time variations.