Adapter board and method for manufacturing same, probe card, method for inspecting semiconductor wafer, and method for manufacturing semiconductor device

• US 20100009471A1
• Filed: 01/22/2009
• Published: 01/14/2010
• Est. Priority Date: 07/10/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Mizoguchi, Osamu
• Granted Patent: US 7,868,469 B2
• Time in Patent Office: Days
• US Class Current: 438/15
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09436 Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 3/244 Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

An adapter board includes a package substrate having a first surface and a second surface and further including a board having wirings formed therein, pads disposed in the device side, and the pads disposed in the bump side, an insulating resin layer joined to the first surface, through holes formed in the positions corresponding to the pads in the insulating resin layer, vias formed in the through holes, and pads covering the through holes, wherein the pads are electrically coupled to the pads through the wirings, and the pads are electrically coupled to the pads through the vias.

Claims

1. An adapter board, comprising:

a package substrate, including a board body having a first surface and a second surface and also having a wiring formed in the interior thereof, a first land pad disposed in said first surface and a second land pad disposed in said second surface;

an insulating layer formed over said first surface of said package substrate;

a through hole formed in a position corresponding to said first land pad of said insulating layer;

a conductive member formed in said through hole;

a third land pad covering said through hole and having a bump side without being covered with the insulating layer; and

an external coupling terminal formed in said second land pad,

wherein said first land pad is electrically coupled to said second land pad through said wiring, and

wherein said third land pad is electrically coupled to said first land pad through said conductive member.

2. The adapter board as set forth in claim 1, further comprising a second testing-dedicated pad for applying electrical signal in said second surface,

wherein said first land pad contains a first testing-dedicated pad,

wherein said first testing-dedicated pad is electrically coupled to said second testing-dedicated pad through said wiring, and

wherein an external coupling terminal is formed in said second testing-dedicated pad.

3. The adapter board as set forth in claim 1, wherein said third land pad is covered with an electroconductive protective film.

4. The adapter board as set forth in claim 3, wherein said electroconductive protective film is a gold-plated film.

5. The adapter board as set forth in claim 1, wherein said third land pad is protruded over the surface of said insulating layer.

6. The adapter board as set forth in claim 1, wherein the dimensional area of said third land pad is larger than the dimensional area of said first land pad.

7. The adapter board as set forth in claim 1, wherein an inter-pad distance for said second land pads is larger than an inter-pad distance for said first land pads, and an inter-pad distance for said third land pads is equivalent to an inter-pad distance for said first land pads.

8. A probe card, being capable of electrically coupling a semiconductor wafer with an measuring apparatus, said semiconductor wafer having a large scale integrated circuit (LSI) formed therein, which is an object of a testing, and said measuring apparatus applying electrical signal to said LSI formed in said semiconductor wafer to measure electrical characteristics of said LSI formed in said semiconductor wafer, said probe card comprising:

an adapter board, including;

a package substrate, including a board body having a first surface and a second surface and also having a wiring formed in the interior thereof, a first land pad disposed in said first surface and a second land pad disposed in said second surface;

an insulating layer formed over said first surface of said package substrate;

a through hole formed in a position corresponding to said first land pad of said insulating layer;

a conductive member formed in said through hole;

a third land pad covering said through hole and having a bump side without being covered with the insulating layer; and

an external coupling terminal formed in said second land pad; and

a probe, being electrically coupled to said third land pad and in contact with the land formed in said semiconductor wafer,

wherein said first land pad is electrically coupled to said second land pad through said wiring, and said third land pad is electrically coupled to said first land pad through said conductive member.

9. The probe card as set forth in claim 8, further comprising a second testing-dedicated pad to apply electrical signal in said second surface,

wherein said first land pad contains a first testing-dedicated pad,

wherein said first testing-dedicated pad is electrically coupled to said second testing-dedicated pad through said wiring, and

wherein an external coupling terminal is formed in said second testing-dedicated pad.

10. The probe card as set forth in claim 8, wherein said third land pad is covered with an electroconductive protective film.

11. The probe card as set forth in claim 10, wherein said electroconductive protective film is a gold-plated film.

12. The probe card as set forth in claim 8, wherein said third land pad is protruded from the surface of said insulating layer.

13. The probe card as set forth in claim 8, wherein the dimensional area of said third land pad is larger than the dimensional area of said first land pad.

14. The probe card as set forth in claim 8, wherein an inter-pad distance for said second land pads is larger than an inter-pad distance for said first land pads, and an inter-pad distance for said third land pads is equivalent to an inter-pad distance for said first land pads.

15. A method for manufacturing an adapter board, comprising:

preparing a package substrate including a board body having a first surface and a second surface and also having a wiring formed in the interior thereof, a first land pad disposed in said first surface and a second land pad disposed in said second surface;

forming an insulating layer in said first surface;

forming a through hole in a position corresponding to said first land pad of said insulating layer;

forming a conductive member in said through hole;

covering said through hole with a third land pad; and

forming an external coupling terminal in said second land pad,

wherein said first land pad is electrically coupled to said second land pad through said wiring, and

wherein said third land pad is electrically coupled to said first land pad through said conductive member, and has a bump side without being covered with the insulating layer.

16. The method for manufacturing the adapter board as set forth in claim 15,

wherein said prepared package substrate has a second testing-dedicated pad in said second surface,

wherein said first land pad contains a first testing-dedicated pad,

wherein said first testing-dedicated pad is electrically coupled to said second testing-dedicated pad through said wiring, and

wherein an external coupling terminal is formed in said second testing-dedicated pad.

17. A method for inspecting a semiconductor wafer, using a probe card, being capable of electrically coupling a semiconductor wafer to an measuring apparatus, said semiconductor wafer having a large scale integrated circuit (LSI) formed therein, which is an object of a testing, and said measuring apparatus applying electrical signal to said LSI formed in said semiconductor wafer to measure electrical characteristics of said LSI formed in said semiconductor wafer, said probe card comprising:

an adapter board, including

a package substrate including a board body having a first surface and a second surface and also having a wiring formed in the interior thereof, a first land pad disposed in said first surface and a second land pad disposed in said second surface;

an insulating layer formed over said first surface of said package substrate;

a through hole formed in a position corresponding to said first land pad of said insulating layer;

a conductive member formed in said through hole;

a third land pad covering said through hole and having a bump side without being covered with the insulating layer; and

an external coupling terminal formed in said second land pad, said adapter board providing an electric coupling between said first land pad and said second land pad; and

a probe, being electrically coupled to said third land pad and in contact with the land formed in said semiconductor wafer,

wherein said method comprises;

causing said probe in contact with the land provided in said semiconductor wafer; and

applying electrical signal to said semiconductor wafer to measure electrical characteristics of said semiconductor wafer.

18. The method for inspecting the semiconductor wafer as set forth in claim 17, wherein, before causing said probe in contact with the land provided in said semiconductor wafer, said probe is brought into a floating condition over said third land pad, and then said probe is pressed over said third land pad to cause said probe in contact with said land.

19. A method for manufacturing a semiconductor device, comprising:

preparing two package substrates, each including a board body having a first surface and a second surface and also having a wiring formed in the interior thereof, a first land pad disposed in said first surface and a second land pad disposed in said second surface;

electrically coupling a semiconductor wafer to an measuring apparatus, said semiconductor wafer having a large scale integrated circuit (LSI) formed therein, which is an object of a testing, and said measuring apparatus applying electrical signal to said LSI formed in said semiconductor wafer to measure electrical characteristics of said LSI formed in said semiconductor wafer;

inspecting said semiconductor wafer by using a probe card having one of said prepared two package substrates;

dicing said semiconductor wafer into semiconductor elements containing said LSI; and

packaging said semiconductor element over the other of said prepared two package substrates,

wherein said probe card includes;

an adapter board including;

said one of the package substrates;

an insulating layer formed over said first surface of said one of the package substrates;

a through hole formed in the position corresponding to said first land pad of said insulating layer;

a conductive member formed in said through hole;

a third land pad covering said through hole and having a bump side without being covered with the insulating layer; and

an external coupling terminal formed in said second land pad; and

a probe, being electrically coupled to said third land pad included in said adapter board and in contact with the land formed in said semiconductor wafer;

wherein said inspecting the semiconductor wafer includes;

electrically coupling said third land pad to said land by causing said probe into contact with the land provided in said semiconductor wafer; and

applying electrical signal from said measuring apparatus to said semiconductor wafer to measure electrical characteristics of said semiconductor wafer,

wherein said packaging the semiconductor element includes;

installing said semiconductor element in said first surface of said other package substrate and

providing an electric coupling of said semiconductor element with the first land pad of said other package substrate; and

forming an external coupling terminal over said second land pad of said other package substrate.