MODEL-BASED SCANNER TUNING SYSTEMS AND METHODS

• US 20100010784A1
• Filed: 05/29/2009
• Published: 01/14/2010
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Koonmen, James Patrick, Goossens, Ronaldus Johannes,Gljsbertus, Ye, Jun, Cao, Yu, Shao, Wenjin
• Granted Patent: US 8,571,845 B2
• Time in Patent Office: Days
• US Class Current: 703/1
• CPC Class Codes: B29C 64/386 Data acquisition or data processing for additive manufacturing
• CPC Class Codes: G03F 7/70091 Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
• CPC Class Codes: G03F 7/70458 Mix-and-match, i.e. multiple exposures of the same area using a similar type of exposure apparatus, e.g. multiple exposures using a UV apparatus
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70516 Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
• CPC Class Codes: G03F 7/70525 Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.

Claims

1. A method for tuning a lithographic apparatus using a corresponding model, comprising:

maintaining a lithographic process model characterizing the imaging behavior of the lithographic process for a given layer of a wafer using the lithographic apparatus, subject to changes in a set of tunable parameters on the lithographic apparatus;

generating simulated wafer contour in the given layer using a design layout and the lithographic process model;

identifying discrepancies in the simulated wafer contour against a reference;

quantifying the discrepancies with a cost function; and

performing iterations of the generating and identifying steps to minimize the cost function and obtain a desired degree of convergence of the simulated wafer contour with the reference, wherein at least one tunable parameter of the lithographic apparatus is adjusted prior to performing each iteration.

2. The method of claim 1, wherein the lithographic process model is a sensitivity model.

3. The method of claim 1, wherein the reference is a measured wafer contour from a reference lithographic process dissimilar to the lithographic process, for a set of patterns in the design layout.

4. The method of claim 1, wherein the reference is a simulated wafer contour from a reference lithographic process model dissimilar to the lithographic process model, for a set of patterns in the design layout.

5. The method of claim 1, wherein the reference comprises design target polygons for a set of patterns in the design layout.

6. The method of claim 1, wherein the discrepancies in the simulated wafer contour against the reference are obtained via an OPC verification tool.

7. The method of claim 3 or 4, wherein the difference between an untuned wafer contour and the reference is obtained via a differential process model.

8. The method of claim 1, wherein the cost function comprises imaging metric terms associated with every pattern in a tuning target pattern set.

9. The method of claim 1, wherein the discrepancies in wafer contours result from differences in one or more of optics, mechanics, control and device-specific laser differences of the lithographic apparatus.

10. The method of claim 1, wherein the discrepancies in wafer contours result from differences in one or more of mask, resist, track, and etch differences of the lithographic process.

11. The method of claim 6, wherein the step of identifying discrepancies includes identifying hotspots.

12. The method of claim 11, wherein the hotspots include yield-limiting defects occurring under process variations.

13. The method of claim 11 or 12, wherein the hotspots include patterns in the design layout that are adversely affected by characteristics specific to the lithographic apparatus.

14. The method of claim 1, further comprising calculating tuning offsets to bring critical dimensions for certain patterns in the design layout within predefined tolerances.

15. The method of claim 14, wherein the steps of generating, identifying and calculating are repeated until a plurality of hotspots are eliminated.