Non-intrusive debug port interface
First Claim
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1. A processor, comprising:
- a core configured to control a keyboard;
a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard;
one or more registers; and
a controller configured to transfer signals from the one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.
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Abstract
A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.
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Citations
33 Claims
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1. A processor, comprising:
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a core configured to control a keyboard; a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard; one or more registers; and a controller configured to transfer signals from the one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A processor, comprising:
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at least one multi-purpose output pin; a first unit configured to transfer signals through the multi-purpose output pin; a second unit configured to transfer signals through the multi-purpose output pin; and a controller configured to stall the operation of the first unit, responsive to a determination that a transmission from the second unit through the multi-purpose output pin may interfere with correct operation of the first unit. - View Dependent Claims (18, 19, 20, 21)
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22. A processor, comprising:
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at least one multi-purpose output pin; a first unit configured to transfer signals through the multi-purpose output pin; a second unit configured to transfer signals through the multi-purpose output pin; and a controller configured to initiate transfer of signals from the second unit through the multi-purpose output pin whenever there is a change in the signals provided by the first unit on the multi-purpose output pin and the second unit is not already transferring signals on the multi-purpose output pin. - View Dependent Claims (23, 24, 25, 26)
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27. A method of outputting information from a processor, comprising:
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storing information in one or more registers within a processor; providing keyboard scan signals via a specific pin of a processor; and transmitting the information stored in the one or more registers, via the specific pin of the processor. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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Specification