DEVICE AND METHOD FOR BACKING UP DATA ON NON- VOLATILE MEMORY MEDIA, OF THE NAND FLASH TYPE, DESIGNED FOR ONBOARD COMPUTERS

• US 20100011157A1
• Filed: 06/25/2009
• Published: 01/14/2010
• Est. Priority Date: 07/08/2008
• Status: Abandoned Application

• Current Assignee: Thales SA
• Original Assignee: Thales SA
• Inventors: Charrier, Nicolas, Baig, Matthieu, Tricot, Sebastien
• Application Number:
  US12/491,942
• Publication Number:
  US 20100011157A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

The present invention relates to a device making it possible to manage a flash memory component designed for onboard computers notably in the aviation field. In particular, the invention makes it possible to use NAND flash memory media in fields such as aviation, by virtue of its judicious organisation and management of the flash memory components. On the one hand it makes it possible to optimise and on the other hand to control the lifetime of the flash memories.

Claims

1. Device for backing up data on a non-volatile memory medium of onboard computers, the device comprising:

a microcontroller having a random access memory; and

a flash memory component, wherein the flash memory component comprises;

N backup-dedicated sectors used to backup files and messages, the files associated with one or more of the messages, the backup-dedicated sectors having one or more respective addresses and comprising;

corrupted backup-dedicated sectors; and

uncorrupted backup-dedicated sectors,

wherein the uncorrupted backup-dedicated sectors exhibit a number of completed erasure cycles;

the flash memory component further comprises a master table block comprising;

a corrupted sectors table, to list the addresses of the corrupted backup-dedicated sectors;

a wear levelling table, to list the number of completed erasure cycles associated with each of the uncorrupted backup-dedicated sectors; and

a logbook and message table, comprising a set of file identifiers to identify one or more files, each file containing one or more messages, the logbook and message table making it possible to list the addresses of the backup-dedicated sectors containing the data associated with the messages; and

the backup device further comprises;

a circuit to erase and to recreate the master table block at a different address upon each modification of at least one backup-dedicated sector.

2. Device according to claim 1, wherein the flash memory component has a nominal lifetime, that corresponds to the envisaged lifetime of the flash memory component, wherein the flash memory component has an erasure frequency that corresponds to the average time between two backup-dedicated sector erasure cycles, computed over all the uncorrupted backup-dedicated sectors, the erasure frequency being less than a maximum erasure frequency in order to ensure the nominal lifetime of the flash memory component.

3. Device according to claim 2, wherein the flash memory component has a nominal lifetime of between 20 years and 30 years, further comprising approximately 8000 to 10000 backup-dedicated sectors, each backup-dedicated sector having a guaranteed operation of up to approximately 100000 erasure cycles, wherein the maximum erasure frequency is of the order of 1 per second.

4. Device according to claim 2, wherein a duration of use of the flash memory, corresponding to a sum of the periods during which the flash memory component is powered up, is saved in the master table block, making it possible to determine the erasure frequency of the flash memory component.

5. Device according to claim 2, wherein for predetermined short periods the erasure frequency exceeds the maximum erasure frequency.

6. Device according to claim 1, wherein the flash memory component is of the NAND flash type.

7. Device according to claim 1, wherein:

the master table block comprises a reserved memory space that corresponds to a backup-dedicated sector;

the corrupted sectors table comprises a reserved memory space that is less than or equal to approximately 1% of the memory space reserved for the master table block;

the wear levelling table comprises a reserved memory space of between about 20% and about 30% of the memory space reserved for the master table block; and

the logbook and message table comprises a reserved memory space of between about 30% and about 40% of the memory space reserved for the master table block.

8. Management method for a device for backing up data on a non-volatile memory medium according claim 1, comprising the steps of:

when the flash memory component starts up;

reading all the backup-dedicated sectors;

locating the master table block, designated an old master table block; and

loading, into the random access memory for the microcontroller, the old master table block comprising the corrupted sectors table, the wear levelling table and the logbook and message table;

when a message is written on the flash memory component;

erasing the youngest sector, the youngest sector corresponding to the sector dedicated to the available memory having the smallest number of completed erasure cycles;

writing the message in the youngest sector;

writing a new, up-to-date master table block, by;

erasing the youngest sector and writing the message; and

erasing the old master table block.

9. Method according to claim 8, wherein the reading of all the backup-dedicated sectors for the purpose of locating the master table block culminates initially in the location of several possible master table blocks, wherein the master table block has an identifier associated with its date of last modification, making it possible to identify the correct master table block, that is the most recent.

10. Method according to claim 8, wherein the device has approximately a 10 millisecond time period before ceasing to operate in the event of an electricity supply disconnection, wherein the 10 millisecond time period allows the saving of the master table block, wherein the master table block comprises information to trace the interruption of a possible operation in progress.

11. Method according to claim 8, wherein the management of the flash memory component is provided by a software program that is executed by the microcontroller.

12. Device according to claim 4, wherein the erasure frequency may, for predetermined short periods, exceed the maximum erasure frequency.

13. Device according to claim 4, wherein the flash memory component is of the NAND flash type.

14. Device according to claim 4, wherein:

the master table block comprises a reserved memory space that corresponds to a backup-dedicated sector;

the corrupted sectors table comprises a reserved memory space that is less than or equal to approximately 1% of the memory space reserved for the master table block;

the wear levelling table comprises a reserved memory space of between about 20% and about 30% of the memory space reserved for the master table block; and

the logbook and message table comprises a reserved memory space of between about 30% and about 40% of the memory space reserved for the master table block.

15. Device according to claim 13, wherein:

the master table block comprises a reserved memory space that corresponds to a backup-dedicated sector;

the corrupted sectors table comprises a reserved memory space that is less than or equal to approximately 1% of the memory space reserved for the master table block;

the wear levelling table comprises a reserved memory space of between about 20% and about 30% of the memory space reserved for the master table block; and

the logbook and message table comprises a reserved memory space of between about 30% and about 40% of the memory space reserved for the master table block.

16. Method according to claim 9, wherein the management of said flash memory component is provided by a software program that is present on said microcontroller.

17. Method according to claim 10, wherein the management of said flash memory component is provided by a software program that is present on said microcontroller.