MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD FOR MEMORY SYSTEM

• US 20100011158A1
• Filed: 07/10/2009
• Published: 01/14/2010
• Est. Priority Date: 07/14/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KITAZUME, Toshihiko, SHIRAISHI, Atsushi
• Granted Patent: US 8,266,368 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip 0 and chip 1, each of the chips composed of a large number of memory cells capable of storing two-bit data in one memory cell in units of two types of pages, the memory controller including a NAND I/F with the semiconductor memory section, and a CPU configured to execute writing programs repeatedly for two types of pages in a memory cell which belongs to the chip 0 and thereafter execute writing programs into a memory cell which belongs to the chip 1.

Claims

1. A memory controller, comprising:

a module configured to control an interface with a semiconductor memory section which is made up of a plurality of chips that are composed of a large number of memory cells capable of storing N-bit data (N being an integer ≧

2) in one memory cell in units of N types of pages; and

a control section configured to execute writing programs repeatedly for all of the N types of pages in a memory cell which belongs to one of the chips and thereafter execute writing programs for all of the N types of pages in a memory cell which belongs to another one of the chips in an interleaved manner.

2. The memory controller according to claim 1, wherein the plurality of chips are two chips.

3. The memory controller according to claim 2, wherein the N is 2 or 3.

4. The memory controller according to claim 3, wherein the memory cells are NAND-type flash memory cells.

5. A memory system, comprising:

a semiconductor memory section which is made up of a plurality of chips that are composed of a large number of memory cells capable of storing N-bit data (N being an integer ≧

2) in one memory cell in units of N types of pages; and

a memory controller having a control section configured to, when performing processing for writing data into the semiconductor memory section in an interleaved manner, execute writing programs repeatedly for all of the N types of pages in a memory cell which belongs to one of the memory cells of one of the chips and thereafter execute writing programs for all of the N types of pages in a memory cell which belongs to another one of the chips.

6. The memory system according to claim 5, wherein the plurality of chips are two chips.

7. The memory system according to claim 6, wherein the N is 2 or 3.

8. The memory system according to claim 7, wherein the memory cells are NAND-type flash memory cells.

9. A control method for a memory system, the method comprising:

executing writing programs for all of N types of pages in a memory cell which belongs to one of chips of a semiconductor memory section, the semiconductor memory section being made up of a plurality of chips that are composed of a large number of memory cells capable of storing N-bit data (N being an integer ≧

2) in one memory cell in units of N types of pages; and

further executing writing programs for all of the N types of pages in a memory cell which belongs to another one of the chips.

10. The control method for a memory system according to claim 9, wherein the plurality of chips are two chips.

11. The control method for a memory system according to claim 10, wherein the N is 2 or 3.

12. The control method for a memory system according to claim 11, wherein the memory cells are NAND-type flash memory cells.