CACHE MEMORY

• US 20100011169A1
• Filed: 07/08/2008
• Published: 01/14/2010
• Est. Priority Date: 07/08/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pothireddy, Anil
• Granted Patent: US 8,316,187 B2
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache

Abstract

Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request.

Claims

1. A cache memory comprising:

one or more cache lines of equal size, each said cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and

a predict buffer, of size equal to the size of said cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous said access request.

2. The cache memory of claim 1, wherein said predict-fetch signal is generated by:

comparing a number of successive cache hits generated by access requests from said processor to the same cache block with a predetermined threshold; and

asserting said predict-fetch signal based on said comparison.

3. The cache memory of claim 2, wherein said next block of data from said main memory has an address next to an address of said same cache block in said main memory.

4. The cache memory of claim 2, wherein said generating further comprises:

comparing, if an access request by said processor generates a cache miss, an address of the requested cache block with an address of the cache block in said predict buffer; and

moving the cache block in the predict buffer to one of said cache lines based on said comparison.

5. The cache memory of claim 2, wherein said predict-fetch signal is not asserted if said next cache block is already stored in a cache line of said cache memory.

6. The cache memory of claim 2, wherein said predict-fetch signal is not asserted if said next cache block is already stored in said predict buffer.

7. The cache memory of claim 1, wherein said data from said main memory comprises instructions for said processor.

8. A method of storing a block of data in a cache memory, said method comprising:

comparing a number of successive cache hits generated by access requests from a processor to the same cache block already stored within said cache memory with a predetermined threshold, and

storing, based on said comparison, a next block of data from a main memory in said cache memory, said next block having an address next to the address of said same cache block in said main memory.

9. The method of claim 8, wherein said next block of data is not stored if said next cache block is already stored in a cache line of said cache memory.

10. The method of claim 8, wherein said data from said main memory comprises instructions for said processor.

11. The method of claim 8, wherein said next block of data is stored in a predict buffer in said cache memory, said predict buffer being of size equal to the size of each line in said cache memory.

12. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

one or more cache lines of equal size, each said cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and

a predict buffer, of size equal to the size of said cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous said access request.