PROGRAM VERIFY METHOD FOR OTP MEMORIES

• US 20100011266A1
• Filed: 12/20/2007
• Published: 01/14/2010
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Sidense Corporation (Synopsys Incorporated)
• Inventors: Kurjanowicz, Wlodek
• Granted Patent: US 8,082,476 B2
• Time in Patent Office: Days
• US Class Current: 714/735
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is used for programming selected memory cells. In a program verify operation, the data programmed to the memory cells are read out and stored in the slave latches. In each data register stage, the logic states of both latches are compared to each other, and a status signal corresponding to a program pass condition is generated if opposite logic states are stored in both latches. The master latch in each stage is inverted if programming was successful, in order to prevent re-programming of that bit of data.

Claims

1. A method for executing a program verify operation, comprising:

a) loading program data into a first latch of a register stage coupled to at least one bitline of a memory array;

b) programming a memory cell coupled to the at least one bitline;

c) reading the programmed data of the memory cell coupled to the at least one bitline into a second latch of the register stage;

d) comparing logic states stored in the first latch and the second latch; and

e) providing a local status signal corresponding to a program pass condition if opposite data states are stored in the first latch and the second latch.

2. The method of claim 1, wherein the step of loading includes shifting the program data serially into the first latch, the first latch and the second latch being arranged in a master-slave flip-flop configuration.

3. The method of claim 1, wherein the step of loading includes providing the program data in parallel into the first latch, the first latch and the second latch being arranged in a master-slave flip-flop configuration.

4. The method of claim 2, wherein the first latch is coupled to one of the bitlines prior to the step of programming.

5. The method of claim 3, wherein the step of reading includes sensing the programmed data with a sense amplifier and providing sensed data to the second latch.

6. The method of claim 1, wherein the step of comparing includes providing a single bit output corresponding to the result of comparing.

7. The method of claim 6, wherein the step of comparing further includes combining the single output with a previous local status signal to provide the local status signal, the previous local status signal corresponding to a comparison result from a previous register stage.

8. The method of claim 7, further including inverting the program data stored in the first latch if the second latch stores a data state corresponding to a programmed memory cell.

9. The method of claim 8, wherein the step of comparing further includes comparing the data states of the first latch and another first latch in the previous register stage.

10. The method of claim 9, wherein the step of comparing the data states of the first latch and another first latch in the previous register stage includes providing another local status signal if the first latch and the another first latch have the same predetermined data state, the predetermined data state corresponding to the inverted program data.

11. A method for operating a register stage having a first latch and a second latch arranged in a master-slave flip-flop configuration for storing a first bit of data and a second bit of data respectively, comprising:

a. decoupling the first latch from a serial input terminal and decoupling the second latch from the first latch at substantially the same time while a source clock signal oscillates; and

,

b. initiating a shifting operation on either a high logic level of the source clock or a low logic level of the source clock for shifting one of the first bit of data and the second bit of data.

12. The method of claim 11, wherein the step of decoupling includes turning off a first gating device between the first latch and a serial input terminal and turning off a second gating device between the first latch and the second latch.

13. The method of claim 12, wherein turning off includes driving a first clock signal to an inactive logic level for turning off the first gating device, and driving a second clock signal to the inactive logic level for turning off the second gating device.

14. The method of claim 13, wherein the first clock signal and the second clock signal are driven to the inactive logic level by maintaining a shift enable signal at the inactive logic level while the source clock signal oscillates.

15. The method of claim 12, wherein the step of initiating includes turning on the first gating device while the second gating device is turned off for shifting the second bit of data.

16. The method of claim 15, wherein turning on the first gating device includes driving a first clock signal to an active logic level.

17. The method of claim 16, wherein the first clock signal is driven to the active logic level when a shift enable signal is enabled while the source clock signal is at a first logic level, the second clock signal being driven to an inactive logic level when the shift enable signal is enabled while an inverted source clock signal is at a second logic level.

18. The method of claim 17, wherein the step of initiating includes turning on the second gating device while the first gating device is turned off for shifting the first bit of data.

19. The method of claim 18, wherein turning on the second gating device includes driving the second clock signal to the active logic level.

20. The method of claim 19, wherein the second clock signal is driven to the active logic level when the shift enable signal is enabled while the source clock signal is at the second logic level, the first clock signal being driven to the inactive logic level when the shift enable signal is enabled while an inverted source clock signal is at the first logic level.