RECESSED CHANNEL TRANSISTOR AND METHOD FOR PREPARING THE SAME
First Claim
1. A recessed channel transistor, comprising:
- a semiconductor substrate having a trench isolation structure;
a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate;
two doped regions positioned at two sides of the upper block and above the lower block; and
an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions.
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Accused Products
Abstract
A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.
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Citations
10 Claims
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1. A recessed channel transistor, comprising:
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a semiconductor substrate having a trench isolation structure; a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate; two doped regions positioned at two sides of the upper block and above the lower block; and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification