SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20100013049A1
• Filed: 07/17/2009
• Published: 01/21/2010
• Est. Priority Date: 07/18/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Komori, Yosuke, Fukuzumi, Yoshiaki, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu, Matsuoka, Yasuyuki, Ishiduki, Megumi
• Application Number:
  US12/504,959
• Publication Number:
  US 20100013049A1
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film. Then, the sacrificial material is removed and a contact is buried inside the contact holes. The contact has a step difference.

Claims

1. A semiconductor memory device comprising:

a substrate;

a plurality of multilayer bodies stacked on the substrate, each of multilayer body including a plurality of dielectric films and a plurality of electrode films that are alternately layered, and having an end portion of a staircase shape;

a plurality of interlayer dielectric films provided around the respective multilayer bodies; and

a plurality of contacts buried so as to penetrate through the plurality of interlayer dielectric films and connected to respective end portions of the electrode films,

the contact having a step difference at a position that is located between the interlayer dielectric films.

2. The memory device according to claim 1, further comprising:

a dielectric film located between the contact and the interlayer dielectric films other than the uppermost one of the interlayer dielectric films and formed from a material that is different from the material of the interlayer dielectric films.

3. The memory device according to claim 1, wherein the contact is formed from metal.

4. The memory device according to claim 3, wherein the contact is formed from tungsten.

5. The memory device according to claim 3, further comprising:

a barrier metal layer formed on a surface of the contact.

6. The memory device according to claim 1, wherein the portion of the contact located in each of the interlayer dielectric films has a tapered shape which has a diameter decreasing downward.

7. The memory device according to claim 1, wherein the portion of the contact located in each of the interlayer dielectric films has a barrel shape which has a relatively narrow upper end and lower end and a relatively wide center portion.

8. The memory device according to claim 1, further comprising:

an etching stopper film provided between the interlayer dielectric films and formed from a material that is different from the material of the interlayer dielectric films,

the step being formed at a position in the contact corresponding to the boundary between the etching stopper film and the interlayer dielectric film therebelow.

9. The memory device according to claim 1, wherein as viewed from above, the lower end of the portion of the contact located above the step difference is entirely located inside the upper end of the portion of the contact located below the step difference.

10. The memory device according to claim 1, wherein as viewed from above, the lower end of the portion of the contact located above the step difference is only partly located inside the upper end of the portion of the contact located below the step difference.

11. The memory device according to claim 1, wherein the contact and the electrode film are formed from the same conductive material including a metal, and no barrier metal layer is interposed between the contact and the electrode film.

12. The memory device according to claim 11, wherein the conductive material is silicon-containing aluminum.

13. The memory device according to claim 1, wherein at least one of the contacts is in contact with an edge between the upper surface and the side surface of the electrode film.

14. A method for manufacturing a semiconductor memory device, comprising:

forming a first multilayer body by alternately layering a plurality of dielectric films and a plurality of electrode films on a substrate;

processing an end portion of the first multilayer body into a staircase shape;

forming a first interlayer dielectric film around the first multilayer body;

forming a first contact hole having a diameter decreasing downward in the first interlayer dielectric film so that the first contact hole reaches an end portion of the electrode film;

burying a sacrificial material in the first contact hole;

forming a second multilayer body by alternately layering a plurality of dielectric films and a plurality of electrode films immediately above the first multilayer body;

forming a second interlayer dielectric film around the second multilayer body;

forming a second contact hole having a diameter decreasing downward in the second interlayer dielectric film so that the second contact hole reaches the first contact hole;

removing the sacrificial material; and

burying a contact inside the first contact hole and the second contact hole.

15. The method for manufacturing a memory device according to claim 14, wherein

the forming a first interlayer dielectric film includes:

forming a first etching stopper film on the upper and lateral sides of the first multilayer body;

depositing a first dielectric material entirely on the first etching stopper film, the first dielectric material being different from the dielectric material of the first etching stopper film; and

performing planarization using the first etching stopper film as a stopper, and

the forming a second interlayer dielectric film includes;

forming a second etching stopper film so as to cover the first interlayer dielectric film and the second multilayer body;

depositing a second dielectric material entirely on the second etching stopper film, the second dielectric material being different from the dielectric material of the second etching stopper film; and

performing planarization using the second etching stopper film as a stopper.

16. The method for manufacturing a memory device according to claim 15, wherein

the forming a first contact hole includes:

forming a sub-hole to a depth reaching the first etching stopper film by etching the first dielectric material; and

etching the first etching stopper film exposed to the bottom surface of the sub-hole, and

the forming a second contact hole includes;

forming a sub-hole to a depth reaching the second etching stopper film by etching the second dielectric material; and

etching the second etching stopper film exposed to the bottom surface of the sub-hole.

17. The method for manufacturing a memory device according to claim 14, wherein

the electrode film is formed from silicon doped with acceptor,

the sacrificial material is formed from non-doped silicon, and

the removing the sacrificial material is performed by wet etching using alkaline etchant.

18. The method for manufacturing a memory device according to claim 14, wherein

the burying a contact includes:

depositing a metal film inside the first contact hole and the second contact hole and on the upper surface of the second interlayer dielectric film and the upper surface of the second multilayer body;

replacing at least part of a conductive material contained in the electrode films by a metal contained in the metal film; and

removing the metal film deposited on the upper surface of the second interlayer dielectric film and the upper surface of the second multilayer body.

19. The method for manufacturing a memory device according to claim 18, wherein the metal is aluminum, and the conductive material is silicon.

20. The method for manufacturing a memory device according to claim 14, wherein at least one of the first contact holes reaches an edge between the upper surface and the side surface of the electrode film in the forming a first contact hole.