SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

• US 20100013064A1
• Filed: 04/14/2009
• Published: 01/21/2010
• Est. Priority Date: 07/21/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Hsu, Chain-Hau
• Granted Patent: US 7,829,981 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2201/0715 : provided by an outer layer of PCB
• CPC Class Codes: H05K 2203/1316 : Moulded encapsulation of mounted components
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/4069 : for via connections in organic insulating substrates

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor device package, comprising:

a substrate unit including an upper surface, a lower surface, and a lateral surface disposed adjacent to a periphery of the substrate unit, the substrate unit defining a cut-out portion disposed adjacent to the periphery of the substrate unit;

a grounding element disposed in the cut-out portion and at least partially extending between the upper surface and the lower surface of the substrate unit, the grounding element including a connection surface disposed adjacent to the lateral surface of the substrate unit;

a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element, such that the connection surface of the grounding element is electrically exposed, the package body including exterior surfaces that include a lateral surface, the lateral surface of the package body being substantially aligned with the lateral surface of the substrate unit; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the connection surface of the grounding element,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

2. The semiconductor device package of claim 1, wherein the connection surface of the grounding element is substantially aligned with the lateral surface of the substrate unit.

3. The semiconductor device package of claim 1, wherein the connection surface of the grounding element is substantially planar and has a substantially orthogonal orientation with respect to the upper surface of the substrate unit.

4. The semiconductor device package of claim 1, wherein a height of the grounding element is in the range of 0.5 mm to 3.2 mm, and a width of the grounding element is in the range of 0.05 mm to 1.5 mm.

5. The semiconductor device package of claim 1, wherein the electromagnetic interference shield includes a lateral portion that extends along the lateral surface of the substrate unit.

6. The semiconductor device package of claim 5, wherein a lower end of the lateral portion is substantially aligned with the lower surface of the substrate unit.

7. A semiconductor device package, comprising:

a substrate unit including a first surface and a second opposing surface;

a grounding element at least partially extending between the first surface and the second opposing surface, the grounding element corresponding to a remnant of a grounding post and including a connection surface disposed adjacent to a periphery of the substrate unit;

a semiconductor device disposed adjacent to the first surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the first surface of the substrate unit and covering the semiconductor device and the grounding element, such that the connection surface of the grounding element is electrically exposed, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the connection surface of the grounding element,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

8. The semiconductor device package of claim 7, wherein a lateral profile of the semiconductor device package is substantially planar and is substantially orthogonal with respect to the first surface of the substrate unit.

9. The semiconductor device package of claim 7, wherein the grounding element includes at least one of a solder and an electrically conductive adhesive.

10. The semiconductor device package of claim 7, wherein an area of the connection surface is in the range of 0.2 mm² to 10 mm².

11. The semiconductor device package of claim 7, wherein the substrate unit defines a cut-out portion disposed adjacent to the periphery of the substrate unit, and the grounding element is disposed in the cut-out portion.

12. The semiconductor device package of claim 7, wherein the substrate unit further includes a lateral surface extending between the first surface and the second opposing surface, and the connection surface of the grounding element is substantially aligned with the lateral surface of the substrate unit.

13. The semiconductor device package of claim 12, wherein the exterior surfaces of the package body include a lateral surface, and the lateral surface of the package body is substantially aligned with the lateral surface of the substrate unit.

14. The semiconductor device package of claim 7, wherein the electromagnetic interference shield is a conformal shield that includes at least one of aluminum, copper, chromium, tin, gold, silver, stainless steel, and nickel.

15. The semiconductor device package of claim 7, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer, and the first layer and the second layer include different electrically conductive materials.

16. A method of forming a semiconductor device package, comprising:

providing a substrate including an upper surface, a lower surface, and apertures at least partially extending between the upper surface and the lower surface;

electrically connecting a semiconductor device to the upper surface of the substrate;

applying an electrically conductive material to the apertures to form grounding posts disposed in respective ones of the apertures;

applying a molding material to the upper surface of the substrate to form a molded structure covering the grounding posts and the semiconductor device;

forming cutting slits extending through the molded structure and the substrate, the cutting slits being aligned with the substrate, such that;

(a) the substrate is sub-divided to form a substrate unit;

(b) the molded structure is sub-divided to form a package body disposed adjacent to the substrate unit, the package body including exterior surfaces; and

(c) remnants of the grounding posts correspond to grounding elements disposed adjacent to a periphery of the substrate unit, each of the grounding elements including an exposed connection surface; and

forming an electromagnetic interference shield adjacent to the exterior surfaces of the package body and the connection surfaces of the grounding elements.

17. The method of claim 16, wherein a height of at least one of the apertures is in the range of 0.3 mm to 3 mm, and a width of at least one of the apertures is in the range of 0.3 mm to 3 mm.

18. The method of claim 16, wherein applying the electrically conductive material includes applying at least one of a solder and an electrically conductive adhesive to the apertures.

19. The method of claim 16, further comprising securing the lower surface of the substrate to a tape, and wherein forming the cutting slits is such that the cutting slits extend partially through the tape.

20. The method of claim 16, further comprising securing an upper surface of the molded structure to a tape, and wherein forming the cutting slits is such that the cutting slits extend partially through the tape.