PACKAGING STRUCTURAL MEMBER

• US 20100013081A1
• Filed: 07/20/2009
• Published: 01/21/2010
• Est. Priority Date: 07/18/2008
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: United Test and Assembly Center Limited (UTAC Holdings Ltd.)
• Inventors: SUN, Yi Sheng Anthony, ZHANG, Xue Ren, KOLAN, Ravi Kanth, TOH, Chin Hock
• Granted Patent: US 8,384,203 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Claims

1. A method of assembling devices comprising:

providing a temporary carrier substrate with first and second surfaces, the first surface is prepared with an adhesive;

mating a structural member on the carrier substrate, the structural member comprising a plurality of die package regions, wherein a package region comprises a die attach region surrounded by a peripheral region; and

attaching dies in the die attach regions of the structural member,

wherein through-vias are disposed in the package regions of the structural member, the through-vias comprise a conductive material, the through-vias are electrically coupled to bond pads of the dies.

2. The method of claim 1 wherein:

the die attach regions comprise openings extending through surfaces of the structural member; and

attaching dies include disposing dies in the openings for temporary attachment to the carrier substrate.

3. The method of claim 2 comprises:

encapsulating the dies with a mold compound;

curing the mold compound, wherein the structural member reduces warpage;

removing the temporary support carrier; and

separating the structural member to form individual packages.

4. The method of claim 3 wherein:

a thickness of the structural member is about equal to a thickness of the die to produce top surfaces of the mold compound, die and structural member which are about coplanar;

or

a thickness of the structural member is greater than a thickness of the die to produce top surfaces of the mold compound and structural member which are about coplanar.

5. The method of claim 4 comprises:

forming a top RDL layer on top surfaces of the encapsulated dies; and

forming a bottom RDL layer on bottom surfaces of the encapsulated dies after removing the temporary support carrier, wherein the RDL layers and through vias facilitate stacking of packages.

6. The method of claim 3 wherein a thickness of the structural member is less than a thickness of the die.

7. The method of claim 6 comprises:

forming a top RDL layer on top surfaces of the encapsulated dies; and

forming a bottom RDL layer on bottom surfaces of the encapsulated dies after removing the temporary support carrier, wherein the RDL layers and through vias facilitate stacking of packages.

8. The method of claim 2 wherein through-vias are disposed in the peripheral regions of the package regions.

9. The method of claim 8 comprises:

encapsulating the dies with a mold compound;

curing the mold compound, wherein the structural member reduces warpage;

removing the temporary support carrier; and

separating the structural member to form individual packages.

10. The method of claim 9 wherein:

a thickness of the structural member is about equal to a thickness of the die to produce top surfaces of the mold compound, die and structural member which are about coplanar;

or

a thickness of the structural member is greater than a thickness of the die to produce top surfaces of the mold compound and structural member which are about coplanar.

11. The method of claim 10 comprises:

forming a top RDL layer on top surfaces of the encapsulated dies; and

forming a bottom RDL layer on bottom surfaces of the encapsulated dies after removing the temporary support carrier, wherein the RDL layers and through vias facilitate stacking of packages.

12. The method of claim 1 wherein the structural member comprises a planar surface in which package regions are defined.

13. The method of claim 12 wherein the dies comprises flip chips.

14. The method of claim 12 wherein the structural member serves as an interposer between a die and a substrate of a package.

15. The method of claim 12 wherein the structural member comprises through-vias distributed in the package regions.

16. The method of claim 1 wherein the structural member comprises a material for balancing coefficient of thermal expansion (CTE).

17. The method of claim 1 wherein the structural member facilitates assembling devices in a wafer format.

18. A semiconductor package comprising:

a structural member having first and second major surfaces, the structural member includes

a die attach region defined in the structural member, the die attach region accommodates a die for packaging,

a peripheral region surrounding the die attach region, and

at least one through-via disposed in the structural member, the through-via extending through the first and second surfaces of the structural member.

19. The semiconductor package of claim 18 wherein:

the structural member comprises an opening through the major surfaces;

the die is disposed in the opening; and

through-vias are disposed in the peripheral region.

20. The semiconductor package of claim 18 wherein:

the die is attached to the first major surface of the structural member in the die attach region;

the through-vias are disposed in the structural member in the die attach region; and

the structural member serves as an interposer between the die and a substrate.

21. A method of assembling a device comprising:

providing a temporary carrier substrate with first and second surfaces, the first surface is prepared with an adhesive;

mating a structural member on the carrier substrate, the structural member comprising a die package region, wherein the package region comprises a die attach region surrounded by a peripheral region; and

attaching a die in the die attach region of the structural member, wherein at least one through-via is disposed in the structural member,

wherein through-vias are disposed in the package region of the structural member, the through-vias comprise a conductive material, the through-vias are electrically coupled to bond pads of the die.