CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME

• US 20100013082A1
• Filed: 07/21/2009
• Published: 01/21/2010
• Est. Priority Date: 08/11/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 9,391,021 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 : the item being a discrete passive component
• CPC Class Codes: H01L 2224/24227 : the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

Claims

1. A chip package comprising:

a substrate;

a semiconductor chip joined with a first top surface of said substrate, wherein said semiconductor chip comprises a silicon substrate over said first top surface, a MOS device in or over said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second dielectric layers and over said first and second metal layers, and a first metal bump connected to said second metal layer through a first opening in said passivation layer, wherein said first metal bump comprises a first copper layer having a thickness between 5 and 150 micrometers;

a first polymer layer over said first top surface, over said semiconductor chip, across an edge of said semiconductor chip, on a sidewall of said semiconductor chip and on a sidewall of said first metal bump, wherein said first polymer layer has a second top surface substantially coplanar with a third top surface of said first metal bump;

a third metal layer on said second and third top surfaces and across said edge, wherein said first metal bump is connected to said third metal layer; and

a second polymer layer on said third metal layer, on said first polymer layer and across said edge.

2. The chip package of claim 1, wherein said semiconductor chip further comprises a metal trace over said passivation layer and on a contact point of said second metal layer at a bottom of said first opening, wherein said metal trace comprises a second copper layer having a thickness between 1 and 20 micrometers, wherein said first copper layer is further on said second copper layer.

3. The chip package of claim 2, wherein said metal trace further comprises a titanium-containing layer on said contact point and over said passivation layer, wherein said second copper layer is over said titanium-containing layer.

4. The chip package of claim 2, wherein said semiconductor chip further comprises a third polymer layer on said passivation layer, wherein said metal trace is further on said third polymer layer, and wherein said third polymer layer has a thickness between 3 and 15 micrometers.

5. The chip package of claim 1 further comprising a passive device joined with said substrate, wherein said passive device is connected to said second metal layer through said third metal layer.

6. The chip package of claim 1 further comprising a second metal bump on a contact point of said third metal layer at a bottom of a second opening in said second polymer layer, wherein said second metal bump is connected to said contact point through said second opening, and wherein said second metal bump comprises a tin-containing layer over said second contact point.

7. The chip package of claim 1, wherein said substrate comprises a silicon substrate.

8. The chip package of claim 1, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers.

9. A chip package comprising:

a substrate;

a semiconductor chip joined with a first top surface of said substrate, wherein said semiconductor chip comprises a silicon substrate over said first top surface, a MOS device in or over said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second dielectric layers and over said first and second metal layers, and a first metal bump connected to said second metal layer through a first opening in said passivation layer, wherein said first metal bump comprises a first copper layer having a thickness between 20 and 50 micrometers;

a first polymer layer over said first top surface, over said semiconductor chip, across an edge of said semiconductor chip, on a sidewall of said semiconductor chip and on a sidewall of said first metal bump, wherein said first polymer layer has a second top surface substantially coplanar with a third top surface of said first metal bump;

a third metal layer on said second and third top surfaces and across said edge, wherein said third metal layer comprises a second copper layer over said second and third top surfaces, and wherein said first metal bump is connected to said third metal layer; and

a second polymer layer on said third metal layer, on said first polymer layer and across said edge.

10. The chip package of claim 9, wherein said semiconductor chip further comprises a metal trace over said passivation layer and on a contact point of said second metal layer at a bottom of said first opening, wherein said metal trace comprises a second copper layer having a thickness between 1 and 20 micrometers, wherein said first copper layer is further on said second copper layer.

11. The chip package of claim 10, wherein said metal trace further comprises a titanium-containing layer on said contact point and over said passivation layer, wherein said second copper layer is over said titanium-containing layer.

12. The chip package of claim 10, wherein said semiconductor chip further comprises a third polymer layer on said passivation layer, wherein said metal trace is further on said third polymer layer, and wherein said third polymer layer has a thickness between 3 and 15 micrometers.

13. The chip package of claim 9 further comprising a passive device joined with said substrate, wherein said passive device is connected to said second metal layer through said third metal layer.

14. The chip package of claim 9 further comprising a second metal bump on a contact point of said third metal layer at a bottom of a second opening in said second polymer layer, wherein said second metal bump is connected to said contact point through said second opening, and wherein said second metal bump comprises a tin-containing layer over said second contact point.

15. The chip package of claim 9, wherein said second copper layer has a thickness between 5 and 100 micrometers.

16. The chip package of claim 9, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers.

17. A chip package comprising:

a substrate;

a semiconductor chip joined with a first top surface of said substrate, wherein said semiconductor chip comprises a silicon substrate over said first top surface, a MOS device in or over said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first and second dielectric layers and over said first and second metal layers, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers, and wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening, a metal trace over said passivation layer and on said first contact point, wherein said metal trace comprises a first copper layer having a thickness between 1 and 20 micrometers, and a first metal bump on said metal trace, wherein said first metal bump is connected to said first contact point through said metal trace, wherein said first metal bump comprises a second copper layer having a thickness between 5 and 150 micrometers on said first copper layer;

a first polymer layer over said first top surface, over said semiconductor chip, over said metal trace, across an edge of said semiconductor chip, on a sidewall of said semiconductor chip and on a sidewall of said first metal bump, wherein said first polymer layer has a second top surface substantially coplanar with a third top surface of said first metal bump;

a third metal layer on said second and third top surfaces and across said edge, wherein said third metal layer comprises a third copper layer over said second and third top surfaces; and

a second polymer layer on said third metal layer, on said first polymer layer and across said edge.

18. The chip package of claim 17, wherein said metal trace further comprises a titanium-containing layer on said first contact point and over said passivation layer, wherein said first copper layer is over said titanium-containing layer.

19. The chip package of claim 17, wherein said semiconductor chip further comprises a third polymer layer on said passivation layer, wherein said metal trace is further on said third polymer layer, and wherein said third polymer layer has a thickness between 3 and 15 micrometers.

20. The chip package of claim 17, wherein said second copper layer has a thickness between 20 and 50 micrometers.

21. The chip package of claim 17 further comprising a second metal bump on a second contact point of said third metal layer at a bottom of a second opening in said second polymer layer, wherein said second metal bump is connected to said second contact point through said second opening, and wherein said second metal bump comprises a tin-containing layer over said second contact point.

22. The chip package of claim 17, wherein said third metal layer further comprises a titanium-containing layer under said third copper layer and on said second and third top surfaces.

23. The chip package of claim 17, wherein said third copper layer has a thickness between 5 and 100 micrometers.