DC TEST RESOURCE SHARING FOR ELECTRONIC DEVICE TESTING

• US 20100013503A1
• Filed: 07/15/2008
• Published: 01/21/2010
• Est. Priority Date: 07/15/2008
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Huebner, Michael W.
• Granted Patent: US 7,924,035 B2
• Time in Patent Office: Days
• US Class Current: 324/757.30
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A test system can include contact elements for making electrical connections with test points of a DUT. The test system can also include a DC test resource and a signal router, which can be configured to switch a DC channel from the DC test resource between individual contact elements in a group of contact elements.

Claims

1. A probe card assembly comprising:

an electrical interface to a plurality of DC channels to a tester;

a plurality of probes disposed to contact test points on an electronic device to be tested; and

a first signal router configured to connect selectively a first one of the DC channels to any one of a first group of a plurality of the probes.

2. The probe card assembly of claim 1, wherein the electrical interface is also to a plurality of AC channels to the tester.

3. The probe card assembly of claim 2 further comprising a plurality of electrical paths through the probe card assembly connecting ones of the AC channels to ones of a second group of the plurality of probes.

4. A probe card assembly comprising:

an electrical interface to a plurality of DC channels to a tester;

a plurality of probes disposed to contact test points on an electronic device to be tested;

a signal router configured to connect one of the DC channels to a group of a plurality of the probes;

a plurality of current sensors each configured to sense a level of current flowing between one of the probes in the group of probes and the DC channel.

5. The probe card assembly of claim 4, wherein each of the current sensors is further configured to open a switch between the one of the probes in the group and the DC channel if the sensed current exceeds a predetermined current level.

6. The probe card assembly of claim 5 further comprising a controller configured to program selectively the predetermined current level.

7. A test system for testing an electronic device having a plurality of test points, comprising:

a plurality of contact elements configured to make electrical connections with corresponding ones of the plurality of test points;

a DC test resource; and

a signal router configured to switch selectively connection of a DC channel from the DC test resource between contact elements in a group of multiple ones of the contact elements.

8. The test system of claim 7, wherein the DC test resource comprises a measurement device being one of a voltmeter or an ammeter.

9. The test system of claim 7, wherein:

the electronic device comprises a plurality of semiconductor dies,

the contact points are bond pads of the semiconductor dies, and

the contact elements are probes configured to make pressure electrical connections with the bond pads.

10. The test system of claim 7, further comprising a probe card assembly, wherein the signal router is disposed on the probe card assembly and the plurality of contact elements are supported by the probe card assembly.

11. The test system of claim 10, wherein the DC test resource is disposed on the probe card assembly.

12. The test system of claim 7, wherein the electronic device is a semiconductor wafer comprising a plurality of dies, and a first contact element of the group of contact elements is disposed to contact a test point of a first of the dies, and a second contact element of the group of contact elements is disposed to contact a test point of a second of the dies.

13. The test system of claim 7, wherein the electronic device is a semiconductor wafer comprising a plurality of dies, and a first contact element of the group of contact elements is disposed to contact a first test point of one of the dies, and a second contact element of the group of contact elements is disposed to contact a second test point of the same one of the dies.

14. A process of testing an electronic device, comprising:

bringing a plurality of contact elements into contact with test points of an electronic device;

electrically connecting a DC test resource to a selected first contact element in a group of multiple ones of the plurality of contact elements;

performing a first DC test on the electronic device by communicating a DC test signal from the DC test resource through the first contact element; and

electrically switching the DC test resource to a selected second different contact element in the group of multiple ones of the plurality of contact elements; and

performing a second DC test on the electronic device by communicating a DC test signal from the DC test resource through the second contact element.

15. The method of claim 14, wherein the electronic device is a semiconductor wafer comprising a plurality of dies, and the bringing comprises bringing the first one of the plurality of contact elements into contact with a first one of the dies and the second one of the plurality of contact elements into contact with a second one of the dies.

16. The method of claim 15, wherein:

the performing a first DC test comprises performing the first DC test on the first die; and

the performing a second DC test comprises performing the second DC test on the second die.

17. The method of claim 16, wherein the first DC testing comprises performing at least one of a short circuit test, an open circuit test, a leakage current test, and a standby current test.

18. The method of claim 17, wherein the second DC testing comprises performing at least one of a short circuit test, an open circuit test, a leakage current test, and a standby current test.

19. The method of claim 14, wherein the DC test signal is a trimming signal, the method further comprising:

varying the trimming signal; and

monitoring a performance of the electronic device.

20. The method of claim 19 further comprising:

determining a value of the trimming signal at which the performance of the electronic device is substantially optimal; and

setting the electronic device to generate an internal signal with a value substantially the same as the determined value of the trimming signal.