MOSFET Switch with Embedded Electrostatic Charge

• US 20100013552A1
• Filed: 02/27/2009
• Published: 01/21/2010
• Est. Priority Date: 07/15/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun
• Granted Patent: US 8,310,001 B2
• Time in Patent Office: Days
• US Class Current: 327/581
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A vertical device structure includes a volume of semiconductor material, laterally adjoining a trench having insulating material on sidewalls thereof. A gate electrode within the trench is capacitively coupled through the insulating material to a first portion of the semiconducting material. Some portions of the insulating material contain fixed electrostatic charge in a density high enough to invert a second portion of the semiconductor material when no voltage is applied. The inverted portions can be used as induced source or drain extensions, to assure that parasitic are reduced without increasing on-resistance.

Claims

1. (canceled)

5. A device comprising:

a trench having a dielectric material on sidewalls thereof;

semiconductor material adjacent to said trench;

a gate electrode capacitively coupled through said dielectric material to a first portion of said semiconductor material;

a source electrode adjoining a second portion of said semiconductor material which adjoins said first portion of said semiconductor material;

wherein said dielectric material has at least some portions containing fixed electrostatic charge with a charge density at least sufficient to deplete said second portion of said semiconductor material in the absence of applied voltage.

2. The device structure of claim 5, further comprising a source region, wherein an upper surface of said dielectric material is flush with an upper surface of said source region.

3. The device structure of claim 5, further comprising a body contact region adjoining said semiconductor material.

4. The device structure of claim 2, further comprising a source region and a drain region, separated from each other by at least said first portion of said semiconductor material.

6. The device of claim 5, wherein said dielectric material below the gate electrode is substantially thicker than the dielectric material between the gate electrode and the semiconductor material.

7. The device of claim 5, wherein an upper surface of said dielectric material is above an upper surface of said source electrode.

8. The device of claim 5, wherein an upper surface of said dielectric material is flush with an upper surface of said source electrode.

9-10. -10. (canceled)

11. A semiconductor active device comprising:

a source region of a first conductivity type, positioned in proximity to a first trench in semiconductor material;

a second conductivity type body region at least partly underlying said source region, and at least partly adjoining said trench;

an insulated gate electrode inside part of said trench, and capacitively coupled to said body region at a sidewall of said trench to controllably invert said body region at said sidewall and thereby allow majority carriers to flow from said source region through said body region;

a distribution of net electrostatic charge located in said trench at at least some locations where said gate electrode is not present, in a density sufficient to invert at least part of said body region; and

a first conductivity type drain region underlying at least part of said body region.

12. The device of claim 11, wherein said trench below the insulated gate electrode is substantially thicker than the trench between the gate electrode and the semiconductor material.

13. The device of claim 11, wherein said source electrode is vertically offset from said gate electrode.

14. The device of claim 11, wherein said insulated gate electrode includes a smooth transition region at a bottom edge of said insulated gate electrode.

15. The device of claim 13, wherein said insulated gate electrode includes a smooth transition region at a bottom edge of said insulated gate electrode.

18. The device of claim 11, wherein the body region adjoining dielectric material predominantly comprising silicon dioxide.

19. The device of claim 11, said insulated gate electrode includes a polycide layer.

20. The device of claim 18, further comprising a fixed electrostatic charge in the dielectric material near the gate electrode.

33. The semiconductor device structure of claim 11, further comprising a recessed field plate.

34. The semiconductor device structure of claim 11, further comprising trench contacts.

16-17. -17. (canceled)

21-32. -32. (canceled)

35. -44. (canceled)

45. A method for operating a semiconductor device, comprising the actions of:

controlling majority carrier flow from a source region, through a body region and into a drift region, using voltages applied to a gate electrode which is capacitively coupled to at least part of said body region to define a channel therein; and

statically inverting a portion of said body, using permanent electrostatic charge at a semiconductor/dielectric interface of said body region, to thereby form an induced source extension therein, which connects said source region to said channel.

46. The method of claim 45, further comprising statically inverting a lower portion of said body, using permanent electrostatic charge at a semiconductor/dielectric interface of said body region, to thereby form an induced drain extension therein, which connects said drift region to said channel.

47. The method of claim 45, further comprising depleting a portion of said drift region, in proximity to a trench which contains said gate, using permanent electrostatic charge at a semiconductor/dielectric interface between said trench and said drift region.

48-49. -49. (canceled)