PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY

• US 20100013973A1
• Filed: 07/16/2008
• Published: 01/21/2010
• Est. Priority Date: 07/16/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Krishnasamy, Rajendran, Rassel, Richard J., Ellis-Monaghan, John J., Adkisson, James W., Musante, Charles F., Mulugeta, Solomon
• Granted Patent: US 8,009,216 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

Claims

1. A semiconductor structure for an image sensor pixel, said semiconductor structure comprising:

a photosensitive diode structure;

a first transistor including a diffusion region and a first channel, wherein said diffusion region is a source region of said first transistor and is of integral construction with a terminal of said photosensitive diode structure;

a second transistor including a second channel located in proximity to said first channel, wherein said second channel is electrically coupled to said first channel to enable formation of a merged channel including said first channel and said second channel; and

a plurality of frame transfer transistors including a plurality of frame transfer channels, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each of said plurality of frame transfer channels is located in proximity with another of said plurality of frame transfer channels to enable formation of a merged channel including two neighboring frame transistor channels.

2. The semiconductor structure of claim 1, further comprising a set of four metal lines and a set of metal vias, wherein each of said set of four metal lines connects gate electrodes of every fourth frame transfer transistor among said plurality of frame transfer transistors through a subset of said metal vias, and wherein each of said four metal lines connects a different subset of said plurality of frame transfer transistors.

3. The semiconductor structure of claim 1, further comprising a set of three metal lines and a set of metal vias, wherein each of said set of three metal lines connects gate electrodes of every third frame transfer transistor among said plurality of frame transfer transistors through a subset of said metal vias, and wherein each of said three metal lines connects a different subset of said plurality of frame transfer transistors.

4. The semiconductor structure of claim 1, further comprising a global reset transistor including a global reset transistor source region directly connected to said terminal of said photosensitive diode and a global reset transistor drain region directly connected to a power supply source.

5. The semiconductor structure of claim 1, further comprising:

a transfer gate transistor including a transfer gate channel located in proximity with a last frame transfer channel to enable formation of another merged channel including said last frame transistor channel and said transfer gate channel; and

a source follower transistor including a source follower transistor gate electrode connected to said floating diffusion region by a set of metal interconnect structures.

6. The semiconductor structure of claim 5, further comprising:

another photosensitive diode structure;

a third transistor including another diffusion region and a third channel, wherein said other diffusion region is a source region of said third transistor and is of integral construction with a terminal of said other photosensitive diode structure;

a fourth transistor including a fourth channel located in proximity to said third channel, wherein said fourth channel is electrically coupled to said third channel to enable formation of another merged channel including said third channel and said fourth channel; and

another plurality of frame transfer transistors including another plurality of frame transfer channels, wherein each of said other plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each of said other plurality of frame transfer channels is located in proximity with another of said other plurality of frame transfer channels to enable formation of a merged channel including two neighboring frame transistor channels; and

another transfer gate transistor including another transfer gate channel located in proximity with another last frame transfer channel to enable formation of another merged channel including said other last frame transistor channel and said other transfer gate channel.

7. A semiconductor circuit for an image sensor pixel, said semiconductor circuit comprising:

a photosensitive diode;

a first transistor having a first channel, wherein a source of said first transistor is a terminal of said photosensitive diode;

a second transistor having a second channel which is configured to enable formation of a merged channel including said first channel and said second channel; and

a plurality of frame transfer transistors including a plurality of frame transfer channels, wherein each of said plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each neighboring pair of said plurality of frame transfer channels is configured to enable formation of a merged channel including two neighboring frame transistor channels.

8. The semiconductor circuit of claim 7, wherein gates of every fourth frame transfer transistor among said plurality of frame transfer transistors are electrically shorted, and wherein gates of adjoining frame transfer transistors are electrically disconnected.

9. The semiconductor circuit of claim 7, wherein gates of every third frame transfer transistor among said plurality of frame transfer transistors are electrically shorted, and wherein gates of adjoining frame transfer transistors are electrically disconnected.

10. The semiconductor circuit of claim 7, further comprising a global reset transistor, wherein a source of said global reset transistor is directly connected to said terminal of said photosensitive diode and a drain of said global reset transistor drain is directly connected to a power supply source.

11. The semiconductor circuit of claim 7, further comprising:

a transfer gate transistor including a transfer gate channel configured to enable formation of another merged channel including a last frame transistor channel and said transfer gate channel; and

a source follower transistor, wherein a gate of said source follower transistor is directly connected to a drain of said transfer gate transistor.

12. The semiconductor circuit of claim 11, further comprising:

another photosensitive diode;

a third transistor having a third channel, wherein a source of said third transistor is a terminal of said other photosensitive diode;

a fourth transistor having a fourth channel which is configured to enable formation of another merged channel including said third channel and said fourth channel;

another plurality of frame transfer transistors including another plurality of frame transfer channels, wherein each of said other plurality of frame transfer transistors is serially connected among one another and comprises a gate electrode and a frame transfer channel, and wherein each neighboring pair of said other plurality of frame transfer channels is configured to enable formation of a merged channel including two neighboring frame transistor channels; and

another transfer gate transistor including another transfer gate channel configured to enable formation of yet another merged channel including another last frame transistor channel and said other transfer gate channel.

13. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, said design structure comprising:

a first data representing a photosensitive diode;

a second data representing a first transistor in direct serial connection with said photosensitive diode, wherein said first transistor having a first channel, and wherein a source of said first transistor is a terminal of said photosensitive diode;

a third data representing a second transistor in direct serial connection with said first transistor, wherein said second transistor having a second channel configured to enable formation of a merged channel including said first channel and said second channel; and

a fourth data representing a plurality of frame transfer transistors serially connected thereamongst and in direct serial connection with said second transistor.

14. The design structure of claim 13, further comprising a fifth data representing an electrical connection between gate electrodes of every fourth frame transfer transistor among said plurality of frame transfer transistors, wherein gates of adjoining frame transfer transistors are electrically disconnected.

15. The design structure of claim 13, further comprising a fifth data representing an electrical connection between gate electrodes of every third frame transfer transistor among said plurality of frame transfer transistors, wherein gates of adjoining frame transfer transistors are electrically disconnected.

16. The design structure of claim 13, wherein said design structure comprises a netlist.

17. The design structure of claim 13, wherein said design structure resides on storage medium as a data format used for exchange of layout data of integrated circuits.

18. The design structure of claim 13, further comprising a sixth data representing a global reset transistor directly connected to said photosensitive diode a power supply source.

19. The design structure of claim 13, further comprising:

a seventh data representing a transfer gate transistor in direct serial connection with a plurality of frame transfer transistors; and

an eighth data representing a source follower transistor, wherein a gate of said source follower transistor is directly connected to a drain of said transfer gate transistor.

20. The design structure of claim 19, further comprising:

a ninth data representing another photosensitive diode;

a tenth data representing a third transistor in direct serial connection with said other photosensitive diode;

an eleventh data representing a fourth transistor in direct serial connection with said third transistor;

a twelfth data representing another plurality of frame transfer transistors serially connected thereamongst and in direct serial connection with said fourth transistor; and

a thirteenth data representing another transfer gate transistor in direct serial connection with said other plurality of frame transfer transistors and with said transfer gate transistor.