Power Device With Trenches Having Wider Upper Portion Than Lower Portion

• US 20100015769A1
• Filed: 09/25/2009
• Published: 01/21/2010
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Becky Losee, Dean Probst, Robert Herrick
• Inventors: Probst, Dean, Herrick, Robert, Losee, Becky
• Granted Patent: US 7,799,636 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain. The remaining portions of the first doped region adjacent the trench sidewalls form source regions which are self-aligned to the trenches.

Claims

1. A method of forming a semiconductor device, comprising:

forming a masking layer over a silicon layer, the masking layer having openings through which surface areas of the silicon layer are exposed;

isotropically etching the silicon layer through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each bowl-shaped portion having a middle portion and outer portions extending directly underneath the masking layer, the outer portions forming outer sections of corresponding trenches;

removing additional portions of the silicon layer through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches;

forming a first doped region of a first conductivity type in an upper portion of the silicon layer;

forming an insulating layer within each trench, the insulating layer in each trench extending directly over a portion of the first doped region adjacent each trench sidewall; and

removing silicon from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain, the remaining portions of the first doped region adjacent the trench sidewalls forming source regions which are self-aligned to the trenches.

2. The method of claim 1 wherein a top surface of the insulating layer is substantially coplanar with a top surface of the first doped region.

3. The method of claim 1 wherein the step of removing exposed silicon forms a contact opening between every two adjacent trenches.

4. The method of claim 3 further comprising:

prior to forming the first doped region, forming a second doped region of a second conductivity type in the upper portion of the silicon layer.

5. The method of claim 4 further comprising:

implanting dopants through the contact openings to form a heavy body region of a second conductivity type in the second doped region.

6. The method of claim 5 further comprising:

forming a metal layer to electrically contact the source regions and the heavy body region through the contact opening.

7. The method of claim 1 further comprising:

prior to forming the insulating layer, forming a gate electrode partially filling each trench.

8. A method of fabricating a semiconductor device, comprising:

forming a masking layer over a silicon layer, the masking layer having openings through which surface areas of the silicon layer are exposed;

isotropically etching the silicon layer through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each bowl-shaped portion having a middle portion and outer portions extending directly underneath the masking layer, the outer portions forming outer sections of corresponding trenches;

removing additional portions of the silicon layer through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches;

forming a gate electrode partially filling each trench;

forming a first doped region of a first conductivity type in an upper portion of the silicon layer;

forming an insulating layer within each trench such that a top surface of the insulating layer is substantially coplanar with a top surface of the first doped region, each trench having a contour such that the insulating layer in each trench extends directly over a portion of the first doped region adjacent each trench sidewall; and

removing exposed silicon from between adjacent trenches such that;

     1) a contact opening is formed between every two adjacent trenches, and

     2) of the first doped region, only the portion adjacent each trench sidewall remains, the portion of the first doped region remaining adjacent each trench sidewall forming a source region.

9. The method of claim 8 wherein the step of removing exposed silicon is carried out without using a mask so that the contact opening between every two adjacent trenches and the portion of the first doped region remaining adjacent each trench sidewall are self-aligned.

10. The method of claim 8 further comprising:

prior to forming the first doped region, forming a second doped region of a second conductivity type in the upper portion of the silicon layer.

11. The method of claim 10 further comprising:

implanting dopants through the contact openings to form a heavy body region of a second conductivity type in the second doped region between adjacent trenches.

12. The method of claim 11 further comprising:

forming a metal layer to electrically contact the source regions and the heavy body region through the contact opening.