DYNAMIC SCHOTTKY BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE

• US 20100015802A1
• Filed: 09/28/2009
• Published: 01/21/2010
• Est. Priority Date: 10/22/2003
• Status: Active Grant

• Current Assignee: Avolare2 LLC
• Original Assignee: Avolare2 LLC
• Inventors: Snyder, John P., Larson, John M.
• Granted Patent: US 8,058,167 B2
• Time in Patent Office: Days
• US Class Current: 438/664
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Claims

1. A method of manufacturing a MOSFET device for regulating a flow of electrical current, the method comprising:

providing a gate electrode on a semiconductor substrate;

exposing the semiconductor substrate in an area proximal to the gate electrode;

etching the semiconductor substrate on the exposed area using an at least partially isotropic etch;

depositing a thin film of metal in the etched area of the semiconductor substrate; and

reacting the metal with the semiconductor substrate such that at least one of a Schottky or Schottky-like source electrode and drain electrode is formed.

2. The method of claim 1 wherein the etching step is performed using an etch having a lateral etch rate of from approximately one-tenth to ten times of a vertical etch rate.

3. The method of claim 1 wherein the etching step is performed using an etch having approximately the same lateral and vertical etch rates.

4. The method of claim 1 wherein the gate electrode is provided by the steps comprising:

providing a thin insulating layer on the semiconductor substrate;

depositing a thin conducting film on the thin insulating layer;

patterning and etching the thin conducting film to form the gate electrode; and

forming at least one thin insulating layer on at least one sidewall of the gate electrode.

5. The method of claim 1 further comprising removing unreacted metal from the MOSFET device after forming the Schottky or Schottky-like source and drain electrodes.

6. The method of claim 1 wherein the reacting step is performed by thermal annealing.

7. The method of claim 1 wherein the source electrode and the drain electrode are formed from a member of the group consisting of:

Platinum Silicide, Palladium Silicide and Iridium Silicide, and channel dopants in the semiconductor substrate are selected from the group consisting of;

Arsenic, Phosphorous, and Antimony.

8. The method of claim 1 wherein the source electrode and the drain electrode are formed from a member of the group consisting of the rare-earth silicides, and channel dopants in the semiconductor substrate are selected from the group consisting of Boron, Indium, and Gallium.

9. The method of claim 1 wherein Schottky or Schottky-like contact is formed at least in areas adjacent to a channel between the source and drain electrodes.

10. The method of claim 1 wherein an entire surface of the at least one of the source electrode and the drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate.

11. The method of claim 1 wherein before the step of providing the gate electrode, dopants are introduced into the semiconductor substrate.

12. The method of claim 1 wherein the semiconductor substrate has a channel dopant concentration that varies significantly in a vertical direction and is generally constant in a lateral direction.

13. A method of manufacturing a device for regulating a flow of electrical current, the method comprising:

exposing a semiconductor substrate in an area proximal to a gate electrode;

etching the semiconductor substrate on the exposed area using an at least partially isotropic etch; and

depositing and thermally annealing a thin film of metal with the semiconductor substrate such that a Schottky or Schottky-like source electrode and drain electrode is formed.

14. The method of claim 13 wherein the etching step is performed using an etch having a lateral etch rate of from approximately one-tenth to ten times of a vertical etch rate.

15. The method of claim 13 wherein the etching step is performed using an etch having approximately the same lateral and vertical etch rates.

16. The method of claim 13 wherein the etching step is performed using an etch having lateral and vertical etch rates such that a channel width of the device is reduced by between approximately 1 and 50 percent.

17. The method of claim 13 wherein the semiconductor substrate is heated during the depositing step, to encourage surface diffusion of metal atoms along a surface of the semiconductor substrate.