SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL

• US 20100017042A1
• Filed: 11/29/2006
• Published: 01/21/2010
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Lopata, Douglas D.
• Granted Patent: US 8,234,511 B2
• Time in Patent Office: Days
• US Class Current: 700/286
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A representative digital circuit of the invention has an on-chip, non-volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit.

Claims

1. A device, comprising:

a power controller adapted to control one or more power-supply signals applied to a digital circuit; and

a memory adapted to store speed-binning test data that characterize performance of said digital circuit, wherein the power controller is adapted to access said speed-binning test data to sot one or more levels of said one or more power-supply signals.

2. The invention of claim 1, wherein the power controller is adapted to use said speed-binning test data to customize at least one of adaptive power control and dynamic power control.

3. The invention of claim 1, wherein the speed-binning test data has been generated and stored in said memory during production testing of the digital circuit.

4. The invention of claim 3, wherein the speed-binning data comprise one or more supply voltages at which the digital circuit has passed testing employing one or more respective speed-binning test vectors.

5. The invention of claim 1, wherein the memory is a one-time programmable (OTP) fuse block.

6. The invention of claim 1, wherein the power controller is adapted to (i) determine a speed constraint for a task to be executed by the digital circuit and (ii) specify one or more levels of said one or more power-supply signals for the execution of said task based on said speed constraint.

7. The invention of claim 1, further comprising a sensor adapted to sense temperature of the digital circuit, wherein the power controller is adapted to specify one or more levels of said one or more power-supply signals based on a temperature reading obtained from said sensor.

8. The invention of claim 1, further comprising a power management unit (PMU) adapted to:

receive instructions from the power controller regarding one or more levels of said one or more power-supply signals; and

generate said one or more power-supply signals based on said instructions.

9. The invention of claim 8, wherein the power controller and the PMU comply with a PowerWise™

Interface Specification.

10. The invention of claim 8, wherein:

the device is implemented using a chipset having first and second integrated circuits (ICs);

the memory, the power controller, and the digital circuit are part of the first IC; and

the PMU is part of the second IC.

11. The invention of claim 1, wherein the digital circuit is a digital base-band (DBB) circuit for cellular telephony.

12. A power-management method, comprising:

applying one or more power-supply signals to a digital circuit; and

reading speed-binning test data that characterize performance of said digital circuit from a memory to set one or more levels of said one or more power-supply signals.

13. The invention of claim 12, further comprising:

customizing at least one of adaptive power control and dynamic power control using said speed-binning test data.

14. The invention of claim 12, wherein the speed-binning test data has been generated and stored in said memory during production testing of the digital circuit.

15. The invention of claim 14, wherein the speed-binning test data comprise one or more supply voltages at which the digital circuit has passed testing employing one or more respective speed-binning test vectors.

16. The invention of claim 12, further comprising:

determining a speed constraint for a task to be executed by the digital circuit; and

specifying one or more levels of said one or more power-supply signals for the execution of said task based on said speed constraint.

17. The invention of claim 12, farther comprising:

sensing temperature of the digital circuit; and

specifying one or more levels of said one or more power-supply signals based on the temperature.

18. A method of testing a digital circuit, comprising:

storing in a memory speed-binning test data that characterize performance of the digital circuit, wherein the digital circuit comprises;

the memory; and

a power controller adapted to;

control one or more power-supply signals applied to the digital circuit; and

access said speed-binning test data to set one or more levels of said one or more power-supply signals.

19. The invention of claim 18, further comprising:

selecting a speed-binning test vector;

setting a power-supply signal to a first voltage level;

running the selected speed-binning test vector through the digital circuit at said set voltage level;

determining whether the digital circuit passed a test employing the selected speed-binning test vector at said set voltage level;

if the digital circuit passed said test, setting the selected power-supply signal to a next voltage level; and

repeating the steps of running, determining, and setting to a next voltage level to determine a minimum supply voltage at which the digital circuit is able to pass the test employing the selected speed-binning test vector.

20. The invention of claim 18, wherein the speed-binning test data comprise one or more supply voltages at which the digital circuit has passed testing employing one or more respective speed-binning test vectors.